參數(shù)資料
型號(hào)： MC145225
廠商： Motorola, Inc.
英文描述： Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器)
中文描述： 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器）
文件頁(yè)數(shù)： 11/71頁(yè)
文件大?。?/td> 906K
代理商： MC145225
MC145225 MC145230
11
MOTOROLA RF/IF DEVICE DATA
5. PIN DESCRIPTIONS
5A. DIGITAL PINS
Enb, Din, and Clk
Pins 5, 6, and 7 — Serial Data Port Inputs
The Enb input is used to activate the serial interface to
allow the transfer of data to the device. To transfer data to the
device, the Enb pin must be low during the interval that the
data is being clocked in. When Enb is taken back high
(inactive), data is transferred to the appropriate register
depending either on the data stream length or address bits.
The C, Hr, and N registers can be accessed using either a
unique data stream length (BitGrabber) or by using address
bits (Conventional). The D, Hn , and R registers can only be
accessed using address bits. See Table 1.
The bit stream begins with the MSB and is shifted in on the
low–to–high transition of Clk. The bit pattern is 1 byte (8 bits)
long to access the C register, 2 bytes (16 bits) to access the
Hr register, or 3 bytes (24 bits) to access the N register. A bit
pattern of 4 bytes (32 bits) is used to access the registers
when using address bits. The device has double buffers for
storage of the N and R counter divide ratios. One double
buffer is composed of the Hr register which feeds the R
register. An Hr to R register transfer occurs whenever the N
register is written. The other double buffer is the Hn register
which feeds the N register. An Hn to N register transfer
occurs whenever the N register is written. Thus, new divide
ratios may be presented to the R, N , and N counters
simultaneously.
Transitions on Enb must not be attempted while Clk is
high. This puts the device out of synchronization with the
microcontroller. Resynchronization occurs whenever Enb is
high (inactive) and Clk is low.
Data is retained in the registers over a supply range of 1.8
to 3.6 V. The bit–stream formats are shown in Figures 13
through 18.
LD
Pin 8 — Lock Detectors Output
This signal is the logical AND of the lock detect signals
from both PLL and PLL . For the main PLL, the phase
window that defines “l(fā)ock” is programmable via bit N22. The
phase window for the secondary PLL is not programmable.
If either PLL or PLL is in standby, LD indicates the lock
condition of the active loop only. If both loops are in standby,
the LD output is a static low level.
Each PLL’s lock detector is in the high state when the
respective loop is locked (the inputs to the phase detector
being the same phase and frequency). The lock detect signal
is in the low state when a loop is out of lock. See Figure 19.
Upon power up, the LD pin indicates a not locked
condition. The LD pin is a push–pull CMOS output. If unused,
LD should be left open.
Output A
Pin 9 — Multiple–Purpose Digital Output
Depending on control bits R 21 and R 20, Output A is
selectable by the user as a general–purpose output (either
high or low level), fR (output of main reference counter), fR
(output of secondary reference counter), or a phase detector
pulse indicator for both loops. When selected as
general–purpose output, bit C7 determines whether the
output is a high or low level per Table 2. When configured as
fR, fR, or phase detector pulse, Output A appears as a
normally low signal and pulses high.
Output A is a slew–rate limited CMOS totem–pole output.
If unused, Output A should be left open.
Table 1. Register Access
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NOTE:
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Type
BitGrabber
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BitGrabber
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BitGrabber
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Conventional
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Conventional
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Conventional
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Conventional
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Conventional
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Conventional
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Register
C
Hr
C
Hr
N
D
Hn
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Accessed
Nibble
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—
—
$0
$1
$2
$3
$4
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16
32
32
32
32
32
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Nomenclature
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C7, C6, C5, ..., C0
R15, R14, R13, ..., R0
C7, C6, C5, ..., C0
R15, R14, R13, ..., R0
N23, N22, N21, ..., N0
D15, D14, D13, ..., D0
N 15, N 14, N 13, ..., N 0
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No.
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13
14
13
14
15
18
17
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8
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