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| 型號： | MC145225 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 27/71頁 |
| 文件大?。?/td> | 906K |
| 代理商： | MC145225 |
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MC145225 MC145230
27
MOTOROLA RF/IF DEVICE DATA
Figure 19. Lock Detector Operation
fR vs fV
Phase
Relationship
LD
Output
One fR Period
> LD
Window
< LD
Window
< LD
Window
< LD
Window
< LD
Window
< LD
Window
< LD
Window
> LD
Window
> LD
Window
Locked
Unlocked
NOTES:
1. Illustration shown is for the main loop and applies when the secondary loop is either phase locked or in
standby. The actual detector outputs for each loop are ANDed together at the LD pin.
2. The secondary loop is similar to the above illustration.
3. The approximate lock detect window for the main loop is either 64 or 256 Osce cycles and is programmable
via bit N22. The approximate window for the secondary loop is 64 Osce cycles and is not programmable.
4. The LD output is low whenever the phase difference is more than the lock detect window.
5. The LD output is high whenever the phase difference is less than the lock detect window and continues to
be less than the window for 3 fR periods or more.
LOCK DETECTOR OUTPUT CONDITIONS
fR versus fV Relation
Frequency is the same with phase inside the
LD window
Lock Detector Output
Microcontroller Action
Static high level output
Senses high level and no edges, therefore loop
is locked
Frequency is the same with phase outside
the LD window
Static low level output
Senses low level, therefore loop is unlocked
Frequency is slightly different, thus phase is
changing
Dynamic “chattering” output, output has
transitions
Senses edges, therefore loop is unlocked
Frequency is grossly different
Static low level output
Senses low level, therefore loop is unlocked
NOTE:
For simplicity, this table applies to the main loop. The secondary loop is similar. The detector outputs feed an AND gate whose output is the LD pin.
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