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參數(shù)資料
| 型號： | MC145225 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 51/71頁 |
| 文件大?。?/td> | 906K |
| 代理商： | MC145225 |
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MC145225 MC145230
51
MOTOROLA RF/IF DEVICE DATA
If additional filtering is desired, R1 may be split into two
equal resistors and a capacitor to ground inserted. Since the
closest resistance to one–half of 9 k is 4.7 k
, this value is
chosen for R1a and R1b. The maximum value for the added
capacitance is based on the bandwidth of the original loop
filter.
The general form for the transfer function for the passive
filter shown in Figure 54, can be shown to have the form:
s +
ω
2
(s +
ω
1) (s +
ω
3)
F(s) = Kh
where
(R1a + R1b + R2) C
1
ω
1 =
,
R2C
1
ω
2 =
,
(R1 + R2)
1
R1a R1b + R1a R2
ω
3 =
,
Cc
where
R1 = R1a + R1b
and
ω
3 >
ω
2 .
Since splitting R1 into two equal values, R1a and R1b, and
inserting the capacitance between the junction of R1a and
R1b does not change the position of the pole located at
ω
1,
the value of
ω
1 remains
1
ω
1 =
(R1a + R1b + R2) C
The 0 identified at
ω
2 = 1/R2 C is also unaffected by the
addition of Cc if
ω
3 >
ω
2.
Since
.
=
(R1 + R2) C
1
2
R1
R1a = R1b =
.
the value of Cc can be determined by specifying the value for
ω
3 and using the values already determined for R1 and R2.
The rule of thumb is to choose
ω
3 to be 10 x
ω
B so as not to
impact the original filter.
ω
B can be found as
(2 + 4
ζ
2 + 4
ζ
4)]
ω
B =
ω
n
[1 + 2
ζ
2 +
ω
B = 628.3 rad/s
(2+ 4 (0.707)2 + 4 (0.707)4)]
[1 + 2 (0.707)2
+
= 1.293 x 103 rad/s .
10
ω
B = 12.93 x 103 rad/s .
The circuit for the passive loop filter is shown in Figure 54.
R1 is split into two equal values and Cc inserted at the
junction of R1a and R1b. Using the values defined above, Cc
is determined to be
1
R1a R1b + R1a R2
(R1 + R2)
ω
3
Cc =
(R1 + R2) 10
1
R1a R1b + R1a R2
=
= 10.83 nfd
.
10 nfd
ω
B
ω
3
Figure 54. Passive Loop Filter for PDout
R1a
10 k
C
15 k
10 k
R1b
+
10 n
Cc
V1
IC = 0
50 n
R2
V
0
0
0
Open Loop AC Analysis of the Loop Filter
AC analysis is chosen for the mode of simulation for
PSpice and VSIN is chosen for V1 and is set to produce a 1 V
peak output signal. The simulation is then run and the result
shown in Figure 55.
A Bode plot of the loop filter is obtained which describes
the open loop characteristics of the loop filter. The corner
frequencies of the filter can be modified and the simulation
rerun until the desired wave shape is obtained. Since AC
analysis runs much faster than transient analysis, the AC
open loop analysis of the loop filter is much quicker and
requires less resources than the closed loop transient
analysis.
Closed Loop Filter Simulations Using PSpice
The top level schematic for simulating a simple loop filter
for PDout operating closed loop, is shown in Figure 56. This
filter uses the values calculated above.
The schematic represents the PLL function using the
internal phase detector, PDout, the loop filter calculated
above, and a VCO. The parameter table allows altering the
divider value of N, the maximum current obtained from
PDout, and PDout charge pump voltage from the top level
schematic.
The schematic for the VCO is shown in Figure 57. Analog
behavioral modeling is used rather than discrete transistor
modeling to reduce component count and improve simulation
efficiency.
The behavioral VCO is composed of an integrator that
transforms the input ctrl into the voltage control V(int) and a
sine wave generator function whose frequency is controlled
by V(int). EVALUE and GVALUE functions are used to
perform the transforms. The analog behavioral models, ABM
and ABMI, can also be used.
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