參數(shù)資料
型號： MC145181
廠商： Motorola, Inc.
英文描述： Dual 550/60MHz PLL Frequency Synthesizers with DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙550/60MHzPLL頻率合成器)
中文描述： 雙550/60MHz鎖相環(huán)頻率合成器的DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙550/60MHzPLL頻率合成器）
文件頁數(shù)： 50/71頁
文件大小： 907K
代理商： MC145181
MC145181
50
MOTOROLA RF/IF DEVICE DATA
7D. SECONDARY LOOP FILTER DESIGN
Low Pass Filter Design for PDout
The design of low pass filtering for PDout for the device
can be accomplished using the following design information.
In addition to the example included here, Motorola
Application Note AN1207, also includes examples of active
filtering which may be used to supplement this information.
F(s) =
ω
n =
(R1 + R2)sC + 1
R2sC + 1
C
VCO
R2
PDout
R1
NC(R1 + R2)
R2C +
N
K
φ
KVCO
ζ
= 0.5
ω
n
K
φ
KVCO
Definitions:
N = Total Division Ratio in Feedback Loop
K
φ
(Phase Detector Gain) = VDD/ 4
π
V/radian for PDout
K
φ
(Phase Detector Gain) = VDD/2
π
V/radian for
φ
V
and
φ
R
KVCO (VCO Gain) =
2
π
fVCO
VVCO
For a nominal design starting point, the user might consider a
damping factor
ζ
≈
0.7 and a natural loop frequency
ω
n
≈
(2
π
fR/50), where fR is the frequency at the phase detector
input. Larger
ω
n values result in faster loop lock times and, for
similar sideband filtering, higher fR–related VCO sidebands.
Recommended Reading:
Gardner, Floyd M., Phaselock Techniques (second
edition).New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory
and Design (second edition). New York, Wiley–Interscience,
1980.
Blanchard, Alain, Phase–Locked Loops: Application to
Coherent Receiver Design.New York, Wiley–Interscience,
1976.
Egan, William F., Frequency Synthesis by Phase Lock.
New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers
Theory and Design. Englewood Cliffs, NJ, Prentice–Hall,
1983.
Berlin, Howard M., Design of Phase–Locked Loop
Circuits, with Experiments.Indianapolis, Howard W. Sams
and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook.Blue
Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications
Handbook Chapter 17, pp. 538–586. New York, John Wiley
& Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a
Programmable Calculator,” EDN March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals,
Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola
Semiconductor Products, Inc., Reprinted with permission
from Electronic Design,1987.
AN1207, The MC145170 in Basic HF and VHF Oscillators,
Motorola Semiconductor Products, Inc., 1992.
AN1671, MC145170 PSpice Modeling Kit, Motorola
Semiconductor Products, Inc., 1998.
Example:
Given the following information:
VCO frequency = 45.555 MHz,
Frequency step size = 5 kHz,
VCO gain = 3.4 MHz/V.
Design a loop filter with a damping factor of 0.707.
The VCO is assumed to have a linear response
throughout the range used in this example. The gain for the
VCO has been given as 3.4 MHz/V and is multiplied by
2
π
rad/s/Hz for calculating loop filter values.
KVCO = 2
π
rad/s/Hz x 3.4 MHz/V = 2.136 x 107 rad/s/V .
The gain for the phase detector is defined as
VDD
K
φ
=
V/rad for PDout .
4
π
Using a value for VDD (phase detector supply voltage) of
3.6 V with the output voltage multiplier turned off, the value is
3.6
K
φ
=
= 0.2865 V/rad .
4
π
Let
50
2
π
fr
ω
n =
= 628.3 rad/s
and
45.555 MHz
5 kHz
=
FVCO
Fstep size
N =
= 9111 .
Choosing C = 0.05
μ
F and calculating R1 + R2,
K
φ
KVCO
R1 + R2 =
N C
ω
n2
= 34 k
.
With a damping factor of 0.707,
C
–
= 15 k
,
N
K
φ
KVCO
0.707
0.5
ω
n
R2 =
R1 = (R2 + R1) – R2 = 34 k – 15 k = 19 k
The choice for C is somewhat arbitrary, however, its value
does impact the performance of the loop filter. If possible, a
range of choices for C should be used to calculate potential
loop filters and the resultant filters simulated, as will be
shown below, to determine the best balance.
20 k
.
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