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| 型號： | MC145181 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual 550/60MHz PLL Frequency Synthesizers with DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙550/60MHzPLL頻率合成器) |
| 中文描述： | 雙550/60MHz鎖相環(huán)頻率合成器的DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙550/60MHzPLL頻率合成器） |
| 文件頁數(shù)： | 35/71頁 |
| 文件大?。?/td> | 907K |
| 代理商： | MC145181 |
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MC145181
35
MOTOROLA RF/IF DEVICE DATA
Figure 30. Graphical Analysis of
Optimum Bandwidth
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
d
10
100
1 k
10 k
100 k
1M
Hz
VCO
Optimum Bandwidth
Closed Loop Response
20 x log (Nt)
Crystal Reference
15 dB NF of the Noise
Contribution from Loop
Natural Frequency
Figure 31. Closed Loop Frequency Response
for
ζ
= 1
1.0 k
10
0
10
Hz
–20
–30
–40
–50
–60
0.1
100
1.0
–10
d
3 dB Bandwidth
In summary, follow the steps given below:
Step 1: Plot the phase noise of crystal reference and the
VCO on the same graph.
Step 2: Increase the phase noise of the crystal reference by
the noise contribution of the loop.
Step 3: Convert the divide–by–N to dB (20log 8 x N) and
increase the phase noise of the crystal reference by
that amount.
Step 4: The point at which the VCO phase noise crosses the
amplified phase noise of the crystal reference is the
point of the optimum loop bandwidth. This is
approximately 15 kHz in Figure 30.
Step 5: Correlate this loop bandwidth to the loop natural
frequency per Figure 31. In this case the 3.0 dB
bandwidth for a damping coefficient of 1 is 2.5 times
the loop’s natural frequency. The relationship
between the 3.0 dB loop bandwidth and the loop’s
“natural” frequency will vary for different values of
ζ
.
Making use of the equations defined in Figure 32, a
math tool or spread sheet is useful to select the
values for Ro and Co.
Appendix: Derivation of Loop Filter Transfer Function
The purpose of the loop filter is to convert the current from
the phase detector to a tuning voltage for the VCO. The total
transfer function is derived in two steps.
Step 1 is to find the voltage generated by the impedance of
the loop filter.
Step 2 is to find the transfer function from the input of the
loop filter to its output. The “voltage” times the “transfer
function” is the overall transfer function of the loop filter. To
use these equations in determining the overall transfer
function of a PLL, multiply the filter’s impedance by the gain
filter’s transfer function. Figure 33 contains the transfer
function equations for the second, third, and fourth order PLL
filters.
PSpice Simulation
The use of PSpice or similar circuit simulation programs
can significantly reduce laboratory time when refining a PLL
design. The following describes the use of behavioral
modeling to develop useful models for studying loop filter
performance. In many applications the levels of sideband
spurs can also be studied.
Behavioral modeling is chosen, as opposed to discrete
device modeling, to improve performance and reduce
simulation time. PLL devices can contain several thousand
individual transistors. To simulate at this level can result in
generation of an enormous amount of data when compared
to a simpler behavioral model. For example, a logic NAND
gate can contain several transistors. Each of these requires a
data set for each of the transistor terminals. If a half dozen
transistors are used in the gate design, both current and
voltage measurements for each terminal of each device for
every node in the circuit is calculated. The gate can be
expressed as a behavioral model, which is treated and
simulated as a single device. Since PSpice sees this as a
single rather than multiple devices, the amount of
accumulated data is much less, resulting in a faster
simulation.
For applications using integrated circuits such as PLLs, it
is desirable to investigate the performance of the circuitry
added externally to the integrated circuit. By using behavioral
modeling rather than discrete device modeling to represent
the integrated circuit, the engineer is able to study the
performance of the design without the overhead contributed
by simulating the integrated circuit.
Phase Frequency Detector Model
The model for the phase frequency detector is derived
using the waveforms shown in Figure 20. Two signals are
present at the input of the phase frequency detector. These
are the reference input and the feedback from the VCO
and/or prescaler. The two signals are compared to determine
the lag/lead relationship between the two signals and pulses
generated to represent the leading edge of each signal. A
pulse whose width equals the lead of one input signal over
the other is generated by an RS flip–flop (RSFF). One RSFF
generates a pulse whose width equals the lead of the
reference signal over the feedback signal, and a second
RSFF generates a signal whose width is the lead of the
feedback signal over the reference signal. The logical model
for the phase frequency detector is shown in Figure 34.
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