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參數(shù)資料
| 型號： | MC145181 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual 550/60MHz PLL Frequency Synthesizers with DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙550/60MHzPLL頻率合成器) |
| 中文描述： | 雙550/60MHz鎖相環(huán)頻率合成器的DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙550/60MHzPLL頻率合成器） |
| 文件頁數(shù)： | 43/71頁 |
| 文件大?。?/td> | 907K |
| 代理商： | MC145181 |
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MC145181
43
MOTOROLA RF/IF DEVICE DATA
Figure 45. Behavioral RS Flip–flop
If [V(v1)>=1 & V(v2)<1 & V(In2)<1, 5]
If [V(In2)>=1, 0]
If [V(In3)>=1 & V(In2)<1, 5, 0]
Qout
Q
In1
In2
Delay
1 ns
In3
U1
In2
V1
V2
If [V(Q)>=1, 5, 0]
Charge Pump Model
The schematic used for the charge pump in the
phase–frequency detector model is shown in Figure 46. Each
charge pump is made from two analog behavioral blocks.
The blocks chosen are three input behavioral blocks with
current outputs. The two blocks are connected in push–pull
to generate the appropriate source and sink output. The
output of each block is defined using an “If” statement to
monitor the input signals and generate the correct output at
the appropriate time.
One note about this type of design. SPICE does not limit
the output voltage swing necessary to generate the
programmed current. It is possible to implement values for
the loop filter, which will cause the charge pump to exceed
the rail voltage. To limit the output voltage to prevent
exceeding the value of the rails, the two behavioral blocks,
voltage–controlled switches S1 and S2, and constants
VCPHH and VCPHL are added. S1 and S2 on/off resistance
is set to 1
and 1 x 1012
, and the off/on voltage is set to
0 V and 1 V to correspond to the behavioral blocks. The
values defined by the constants are accessible from the
parameter tables on the top level schematic.
VCO Model
The model used for simulating the VCO is shown in
Figure 47. The VCO is composed of a sine wave generator
and a control element. An analog behavioral block is used as
a sine wave generator and a GVALUE element is used as a
control element. The GVALUE is operated as an integrator.
The output of the integrator is defined as
v(int) = k1 v(ctrl) Qc .
The block designated to provide the feedback to the
phase–frequency detector uses a single input analog
behavioral block. The signal shift generated by V1 in the
phase–frequency detector block is used to define the output
frequency of the behavioral block. In this manner, the
switching of the N and R values for the programmable
counters can be simulated. In the implementation shown, the
two frequencies will be either 25 kHz or 100 kHz when locked
to the reference oscillator.
The other behavioral block is used to generate a VCO
output dependent on the loop, but not contributing to the
operation of the loop. This is used to emulate the actual VCO
output with one modification. “H” has been added to the
equation generating the sine wave. If H is defined as 1, the
sine wave generated will be the same as the expected VCO
output. If H is chosen as some value greater than 1, the
frequency of the output will be reduced accordingly. This is
useful when running simulations designed to show reference
spur levels.
In cases where it is desirable to view reference spur levels,
simulation can become difficult or impossible. For example,
consider the circuit that is being discussed. This circuit
represents the evaluation kit (MC145230EVK) using a VCO
tunable between 733 MHz to 742 MHz, with a step frequency
of 25 kHz.
NOTE
This example is for reference only. The
maximum operating frequency of the MC145181
is 550 MHz. Operation of the VCO at
frequencies greater than 550 MHz requires the
inclusion of additional external division such as a
prescaler.
To obtain useful information from the simulation, a
sampling rate greater than the Nyquist limit must be used
(three to five samples per cycle). This dictates a step size
less than 1/2 nanosecond. Additionally, the reference
frequency is only 25 kHz. To accurately represent the
conditions for spur generation, the simulation time must be
long enough to include a sufficient number of fr periods.
Otherwise, no spurs are generated. In addition, the data file
system is limited to 2 Gbyte, either in the NT 4.0 operating
system or in PSpice itself. If the file exceeds 2 Gbyte, the
data is discarded. To simulate reference spur generation at
730 MHz, a 1 ms simulation time was chosen. The simulation
ran for several hours and generated a data file just under
2 Gbyte. The result is shown in Figure 48. The plot obtained
from the EVK is shown in Figure 49 for comparison.
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