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參數(shù)資料
| 型號(hào)： | MC145181 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual 550/60MHz PLL Frequency Synthesizers with DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙550/60MHzPLL頻率合成器) |
| 中文描述： | 雙550/60MHz鎖相環(huán)頻率合成器的DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙550/60MHzPLL頻率合成器） |
| 文件頁數(shù)： | 15/71頁 |
| 文件大小： | 907K |
| 代理商： | MC145181 |
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MC145181
15
MOTOROLA RF/IF DEVICE DATA
5E. EXTERNAL COMPONENTS
Rx
Pin 17 — Current–Setting Resistor
An external resistor to Gnd at this pin sets a reference
current that is used to determine the current at the
phase/frequency detector outputs PDout–Hi and PDout–Lo.
A value of 2 k
is required.
Cmult
Pin 21 — Voltage–Multiplier Capacitor
An external capacitor to Gnd at this pin is used for the
on–chip voltage multiplier circuit. The value of this capacitor
must be greater than 20 times the value of the largest loop
filter capacitor. For example, if the largest loop filter capacitor
on either the main loop or the secondary loop is 0.01
μ
F, then
a 0.22
μ
F capacitor could be used on the Cmult pin.
To ensure minimum standby supply current drain, the
voltage potential at the Cmult pin must not be allowed to fall
below the potential at the Vpos pins. Therefore, if the
keep–alive oscillator is shut off, the user should tie a large
value resistor (> 10 M
) between the Cmult pin and Vpos. This
resistor should be sized to overcome leakage from Cmult to
Gnd due to the printed circuit board and the external
capacitor. The consequence of not using the resistor is
higher supply current drain in standby. If standby is not used,
the resistor is not necessary. Also, if the keep–alive oscillator
is used, the resistor can be omitted.
Creg
Pin 22 — Regulator Capacitor
An external capacitor to Gnd at this pin is required for the
on–chip voltage regulator. A value of 1
μ
F is recommended.
5F. SUPPLY PINS
DAC Vpos
Pin 2 — Positive Supply Potential for DACs
This pin supplies power to both DACs and determines the
full–scale output of the DACs. The full–scale output is
approximately equal to the voltage at DAC Vpos. The voltage
applied to this pin may be more, less, or equal to the potential
applied to the Vpos pins. The voltage range for DAC Vpos is
1.8 to 3.6 V with respect to the Gnd pins.
If both DACs are not used, DAC Vpos should be tied to the
same potential as Vpos.
Vpos
Pins 11, 24, 26, and 29 — Principal Positive Supply
Potential
These pins supply power to the main portion of the chip.
All Vpos pins must be at the same voltage potential. The
voltage range for Vpos is 1.8 to 3.6 V with respect to the Gnd
pins.
For optimum performance, all Vpos pins should be tied
together and bypassed to a ground plane using a
low–inductance capacitor mounted very close to the device.
Lead lengths and printed circuit board traces between the
capacitor and the IC package should be minimized. (The
very–fast switching speed of the device can cause excessive
current spikes on the power leads if they are improperly
bypassed.)
Gnd
Pins 14, 15, 18, and 31 — Ground
Common ground for the device. All Gnd pins must be at
the same potential and should be tied to a ground plane.
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