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參數(shù)資料
| 型號(hào)： | MC145181 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual 550/60MHz PLL Frequency Synthesizers with DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙550/60MHzPLL頻率合成器) |
| 中文描述： | 雙550/60MHz鎖相環(huán)頻率合成器的DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙550/60MHzPLL頻率合成器） |
| 文件頁數(shù)： | 37/71頁 |
| 文件大?。?/td> | 907K |
| 代理商： | MC145181 |
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MC145181
37
MOTOROLA RF/IF DEVICE DATA
Figure 34. Phase Frequency Detector Logic Diagram
PG1
Pulse Generator
PG2
RSFF2
RSFF1
Ref
In
R
S
P1
Out
In
R
φ
V
φ
Pulse Generator
S
R
P1
Out
In
The behavioral model of the phase frequency detector
shown in Figure 35 is derived using the phase frequency
detector logic diagram. Behavioral models for the pulse
generator, AND gate (Figure 36), and RS flip–flops
(Figure 37) are created using analog behavioral blocks. The
pulse generator is created using a delay block and a “gate”
defined by the behavioral expression:
If [V(v1)
≥
1 & V(v2) , 1, 5, 0]
v1 and v2 represent the two inputs to the block.
This is the behavioral expression for an AND gate with one
input inverted. The addition of the delay element produces a
pulse whose width equals the delay element.
The pulses appearing at the output of HB1 and HB2
(Figure 35) are used to set the flip–flops, RSFF1, and
RSFF2. The leading pulse will set the appropriate flip–flop
resulting in a high at the output of that flip–flop. The output of
this flip–flop will remain high until the arrival of the second (or
lagging) pulse sets the second RS flip–flop. The presence of
a high on both RS flip–flop outputs results in the generation of
the reset pulse. The reset pulse is generated by the analog
behavioral block (configured as an AND gate) and the delay
element. The delay element is necessary to eliminate the
zero delay paradox of input to output to input.
The output of the phase frequency detector is two pulse
trains appearing at R
φ
and V
φ
. When the PLL is locked, the
pulses in both pulse trains will be of minimum width. When
the phase frequency detector is out of lock, one pulse train
will consist of pulses of minimum width while the width of the
pulses in the second train will be equal to the lead/lag
relationship of the input signals. If the Ref input leads ‘In’, the
pulse train at R
φ
will consist of pulses whose width equals the
lead of Ref. If Ref lags ‘In’, the width of the pulses appearing
at V
φ
will equal this lag.
The terms lead and lag used in this explanation represent
an occurrence in time rather than a phase relationship. At any
condition other than locked, one input (either In or Ref), will
be of a higher frequency. This results in the arrival of the
pulse at that input ahead of the pulse at the other input, or
leading. The second then is lagging.
To simulate the operation of the phase frequency detector
in an actual circuit, a charge pump needs to be added. The
behavioral model for this is shown in Figure 38. Two
voltage–to–current behavioral models are used to produce
the charge pump output. Two voltage–controlled switches
with additional behavioral models, monitor the voltage of the
output of the charge pump and clamp to 0 or VCC to simulate
a real circuit.
To ensure the model conforms to the PLL, the delay blocks
in the phase frequency detector should be set to the
expected value as specified by the MC145181 data sheet. In
addition, the charge pump sink and source current behavioral
model should also be set to deliver the desired current and
VCC specified to ensure correct clamping.
Modeling the VCO
The VCO (Figure 39) is also modeled using Analog
Behavioral Modeling (ABM). The model used in the following
examples assumes a linear response; however, the control
voltage equation can be modified as desired. The circuit is
modeled as a sine generator controlled by the control
voltage. The sine generator can be modeled using the
EVALUE function or the ABM function. In Figure 39, the
EVALUE function is used to generate the divided output and
the ABM function is used for the undivided output. Either the
GVALUE or the ABM/I function can be used for the control
voltage.
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