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參數(shù)資料
| 型號： | MC145181 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual 550/60MHz PLL Frequency Synthesizers with DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙550/60MHzPLL頻率合成器) |
| 中文描述： | 雙550/60MHz鎖相環(huán)頻率合成器的DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙550/60MHzPLL頻率合成器） |
| 文件頁數(shù)： | 10/71頁 |
| 文件大?。?/td> | 907K |
| 代理商： | MC145181 |
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MC145181
10
MOTOROLA RF/IF DEVICE DATA
pin, is applied to both phase detectors. An external capacitor
to Gnd is required on the Cmult pin. The other capacitors
required for the multiplier are on–chip.
A capacitor to Gnd is also required on the Creg pin. The
voltage on this pin is equal to the voltage on the Vpos pins
over a supply range of 1.8 V to about 2.5 V. The voltage on
Creg is limited to approximately 2.5 V maximum when the
Vpos pins exceed 2.5 V.
The refresh rate determines the repetition rate that the
capacitors for the voltage multiplier are charged. Refresh is
normally derived off of the signal present at the Osce pin,
through a divider which is part of the voltage multiplier and
regulator circuitry. The refresh rate is controlled via bits in the
R register.
When the reference oscillator circuit is placed in standby,
an on–chip keep–alive oscillator assists in maintaining the
elevated voltage on the phase detectors. The keep–alive
refresh rate is per the spec table in Section 3F.
If desired, the keep–alive oscillator can be inhibited from
turning on, by placing the multiplier in the inactive state via R
register bits. This causes the phase/frequency detector
voltage to bleed off while in standby, but has the advantage of
achieving the lowest supply current if all other sections of the
chip are shut down.
4E. PHASE/FREQUENCY DETECTORS
Detector for Main Loop
The detector for the main loop senses the phase and
frequency difference between the outputs of the R and N
counters. The detector feeds both a high–current charge
pump with output PDout–Hi and a low–current charge pump
with output PDout–Lo.
The charge pumps can be operated in three conventional
manners as controlled by bits in the N register. PDout–Lo can
be enabled with PDout–Hi inhibited. Conversely, PDout–Hi
can be enabled with PDout–Lo inhibited. Both outputs can be
enabled and tied together externally for maximum charge
pump current. Finally, both outputs can be inhibited. In this
last case, they float. The outputs can also be forced to the
floating state by a bit in the C register. This facilitates
introduction of modulation into the VCO input.
The charge pumps can be operated in an adapt mode as
controlled by bits in the N register. The bits essentially
program a timer which determines how long PDout–Hi is
active. After the time–out, PDout–Hi floats and PDout–Lo
becomes active. In addition, a second set of R and N counter
values can be engaged after the time–out. For more
information, see Table 16 and Section 8,
Programmer’s
Guide
.
Detector for Secondary Loop
The detector for the secondary loop senses the phase and
frequency difference between the outputs of the R and N
counters. Detector output PDout is a voltage–type output
with a three–state push–pull driver.
The output can be forced to the floating state by a bit in the
C register. This facilitates introduction of modulation into the
VCO input.
4F. LOCK DETECTORS
Window counters in each of the lock detector circuits
determine the lock detector phase threshold for PLL and
PLL . The window counter divide ratio for the main loop’s lock
detector is controlled via a bit in the N register. The window
counter divide ratio for the secondary loop is not controllable
by the user.
The lock detector window determines a minimum phase
difference which must occur before the Lock Detect pin goes
high. Note that the lock detect signals for each loop drive an
AND gate, which then feeds the LD pin. The LD pin indicates
the condition of both loops, or the one active loop if the other
is in standby. If both loops are in standby, LD is low indicating
unlocked.
4G. DACs
The two independent 8–bit DACs facilitate crystal
oscillator trimming and PA output power control. They are
also suitable for any general–purpose use.
Each DAC utilizes an R–2R ladder architecture. The
output pins, DAC1 and DAC2, are directly connected to the
ladder; that is, there is no on–chip buffer.
The DAC outputs are determined by the contents of the D
register. When a DAC output is zero scale, it is also in a
low–power mode. The power–on reset (POR) circuit
initializes the DACs in the low–power mode upon power up.
4H. GENERAL–PURPOSE OUTPUTS
There are three outputs which may be used as port
expanders for a microcontroller unit (MCU).
Output A is actually a multi–purpose output with a
push–pull output driver. See Table 2 for details.
Output B is a three–state output. The state of Output B
depends on two bits; one of these bits also controls whether
the main PLL is in standby or not. See Table 5 for details.
Output C is an open–drain output. The state of this output
is controlled by one bit per Table 4. Output C is specified with
a guaranteed ON resistance, and thus, may be used in an
analog fashion.
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