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參數(shù)資料
| 型號： | MC145181 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual 550/60MHz PLL Frequency Synthesizers with DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙550/60MHzPLL頻率合成器) |
| 中文描述： | 雙550/60MHz鎖相環(huán)頻率合成器的DAC和電壓倍增器（帶數(shù)模轉換器和電壓乘法器的雙550/60MHzPLL頻率合成器） |
| 文件頁數(shù)： | 14/71頁 |
| 文件大?。?/td> | 907K |
| 代理商： | MC145181 |
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MC145181
14
MOTOROLA RF/IF DEVICE DATA
defaults to positive. Positive polarity is described below. fV is
the output of the main loop’s VCO divider (N counter). fR is
the output of the main loop’s reference divider (R counter).
(a) Frequency of fV > fR or phase of fV leading fR:
current–sinking pulses from a floating state.
(b) Frequency of fV < fR or phase of fV lagging fR:
current–sourcing pulses from a floating state.
(c) Frequency and phase of fV = fR: essentially a floating
state, voltage at pin determined by loop filter.
When the Mode pin is high, negative polarity occurs when
the Pol pin is high. Negative polarity is described below. fV is
the output of the main loop’s VCO divider (N counter). fR is
the output of the main loop’s reference divider (R counter).
(a) Frequency of fV > fR or phase of fV leading fR:
current–sourcing pulses from a floating state.
(b) Frequency of fV < fR or phase of fV lagging fR:
current–sinking pulses from a floating state.
(c) Frequency and phase of fV = fR: essentially a floating
state, voltage at pin determined by loop filter.
These outputs can be enabled and disabled by bits in the
C and N registers. Placing the main PLL in standby (bit C1
= 1) forces the detector outputs to a floating state. In addition,
setting the PD Float bit (bit C4 = 1) forces the detector
outputs to a floating state while allowing the counters to run
for the main PLL. For selection of the outputs, see Table 11.
The phase detector gain (in amps per radian) = PDout
current (in amps) divided by 2
π
.
If a detector output is not used, that pin should be left
open.
N20
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PDout
Pin 23 — Phase/Frequency Detector Output for
Secondary Loop (PLL )
This pin is a three–state voltage output for use as a loop
error signal when combined with an external low–pass loop
filter. The detector is characterized by a linear transfer
function (no dead zone). The polarity of the detector is
controllable. The operation of the detector is described below
and shown in Figure 21.
When the Mode pin is high, positive polarity occurs when
the Pol pin is low. Also, when the Mode pin is low, polarity
defaults to positive. Positive polarity is described below. fV is
the output of the secondary loop’s VCO divider (N counter).
fR is the output of the secondary loop’s reference divider (R
counter.)
(a) Frequency of fV > fR or phase of fV leading fR:
negative pulses from high impedance.
(b) Frequency of fV < fR or phase of fV lagging fR:
positive pulses from high impedance.
(c) Frequency and phase of fV = fR: essentially a
high–impedance state, voltage at pin determined by
loop filter.
When the Mode pin is high, negative polarity occurs when
the Pol pin is high. Negative polarity is described below. fV
is the output of the secondary loop’s VCO divider (N
counter). fR is the output of the secondary loop’s reference
counter (R counter.)
(a) Frequency of fV > fR or phase of fV leading fR:
positive pulses from high impedance.
(b) Frequency of fV < fR or phase of fV lagging fR:
negative pulses from high impedance.
(c) Frequency and phase of fV = fR: essentially a
high–impedance state, voltage at pin determined by
loop filter.
This output can be enabled and disabled by bits in the C
register. Placing the secondary PLL in standby (bit C0 = 1)
forces the detector output to a high–impedance state. In
addition, setting the PD Float bit (bit C3 = 1) forces the
detector output to a high–impedance state while allowing the
counters to run for PLL .
The phase detector gain (in volts per radian) = Cmult
voltage (in volts) divided by 4
π
.
If the secondary loop is not used, PLL should be placed in
standby and PDout should be left open.
5D. ANALOG OUTPUTS
DAC1 and DAC2
Pins 3 and 4 — Digital–to–Analog Converter Outputs
These are independent outputs of the two 8–bit D/A
converters. The output voltage is determined by bits in the D
register. Each output is a static level with an output
impedance of approximately 100 k
.
The DACs may be used for crystal oscillator trimming, PA
(power amplifier) output power control, or other
general–purpose use.
If a DAC output is not used, the pin should be left open.
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