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參數(shù)資料
| 型號(hào)： | M30L0R8000B0ZAQF |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CAP 0.1UF 50V 10% X7R DIP-2 BULK S-MIL-C-39014 |
| 中文描述： | 256兆位（16Mb的x16插槽，多銀行，多層次，多突發(fā)）1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 34/83頁 |
| 文件大?。?/td> | 1363K |
| 代理商： | M30L0R8000B0ZAQF |
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M30L0R8000T0, M30L0R8000B0
34/83
Synchronous Burst Read Suspend.
A
chronous Burst Read operation can be suspend-
ed, freeing the data bus for other higher priority
devices. It can be suspended during the initial ac-
cess latency time
(before data is output) in which
case the initial latency time can be reduced to ze-
ro, or after the device has output data. When the
Synchronous Burst Read operation is suspended,
internal array sensing continues and any previous-
ly latched internal data is retained. A burst se-
quence can be suspended and resumed as often
as required as long as the operating conditions of
the device are met.
A Synchronous Burst Read operation is suspend-
ed when Chip Enable, E, is Low and the current
address has been latched (on a Latch Enable ris-
ing edge or on a valid clock edge). The Clock sig-
nal is then halted at V
IH
or at V
IL
, and Output
Enable, G, goes High.
When Output Enable, G, becomes Low again and
the Clock signal restarts, the Synchronous Burst
Read operation is resumed exactly where it
stopped.
Syn-
WAIT will revert to high-impedance when Output
Enable, G, or Chip Enable, E, goes High.
See
Table 24., Synchronous Read AC Character-
istics
, and
Figure 14., Synchronous Burst Read
Suspend AC Waveforms
, for details.
Single Synchronous Read Mode
Single Synchronous Read operations are similar
to Synchronous Burst Read operations except that
the memory outputs the same data to the end of
the operation.
Synchronous Single Reads are used to read the
Electronic Signature, Status Register, CFI, Block
Protection Status, Configuration Register Status
or Protection Register. When the addressed bank
is in Read CFI, Read Status Register or Read
Electronic Signature mode, the WAIT signal is as-
serted during the X latency, the WAIT state and at
the end of a 4, 8 and 16 Word burst. It is only de-
asserted when output data are valid.
See
Table 24., Synchronous Read AC Character-
istics
, and
Figure 12., Synchronous Burst Read
AC Waveforms
, for details.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M30L0R8000B0ZAQT | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000B0ZAQ | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0 | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000B0 | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30LW128D | 128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30L0R8000B0ZAQT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0ZAQ | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0ZAQE | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0ZAQF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
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