- 您現(xiàn)在的位置：買賣IC網 > PDF目錄359054 > M30L0R8000B0ZAQF (意法半導體) CAP 0.1UF 50V 10% X7R DIP-2 BULK S-MIL-C-39014 PDF資料下載
參數(shù)資料
| 型號： | M30L0R8000B0ZAQF |
| 廠商： | 意法半導體 |
| 英文描述： | CAP 0.1UF 50V 10% X7R DIP-2 BULK S-MIL-C-39014 |
| 中文描述： | 256兆位（16Mb的x16插槽，多銀行，多層次，多突發(fā)）1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 28/83頁 |
| 文件大?。?/td> | 1363K |
| 代理商： | M30L0R8000B0ZAQF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
M30L0R8000T0, M30L0R8000B0
28/83
chronous read operations. When the Valid Clock
Edge bit is Low (set to ’0’) the falling edge of the
Clock is the active edge. When the Valid Clock
Edge bit is High (set to ’1’) the rising edge of the
Clock is the active edge.
Wrap Burst Bit (CR3)
The Wrap Burst bit, CR3, is used to select be-
tween wrap and no wrap. Synchronous burst
reads can be confined inside the 4, 8 or 16 Word
boundary (wrap) or overcome the boundary (no
wrap).
When the Wrap Burst bit is Low (set to ‘0’) the
burst read wraps. When it is High (set to ‘1’) the
burst read does not wrap.
Burst length Bits (CR2-CR0)
The Burst Length bits are used to set the number
of Words to be output during a Synchronous Burst
Read operation as result of a single address latch
cycle.
They can be set for 4 Words, 8 Words, 16 Words
or continuous burst, where all the Words are read
sequentially. In continuous burst mode the burst
sequence can cross bank boundaries.
In continuous burst mode, in 4, 8 or 16 Words no-
wrap, depending on the starting address, the de-
vice asserts the WAIT signal to indicate that a de-
lay is necessary before the data is output.
If the starting address is aligned to an 8 Word
boundary no WAIT states are needed and the
WAIT output is not asserted.
If the starting address is not aligned to the 8 Word
boundary, WAIT will be asserted when the burst
sequence crosses the first 16 Word boundary to
indicate that the device needs an internal delay to
read the successive Words in the array.
WAIT will be asserted only once during a continu-
ous burst access. See also
Table 12., Burst Type
Definition
.
CR14, CR5
and
CR4
are reserved for future use.
相關PDF資料 |
PDF描述 |
|---|---|
| M30L0R8000B0ZAQT | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000B0ZAQ | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0 | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000B0 | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30LW128D | 128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M30L0R8000B0ZAQT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0ZAQ | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0ZAQE | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0ZAQF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復。