參數(shù)資料
型號： M306H7MC-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 8/115頁
文件大?。?/td> 3146K
代理商： M306H7MC-XXXFP
Rev.2.10
Oct 25, 2006
Page 105 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
Figure 10.9
Transmit and Receive Operation
D0 D1
D2 D3
D4 D5 D6
D7
D0 D1
D2 D3 D4 D5 D6 D7
D0 D1 D2 D3
D4 D5 D6
D7
Tc
TCLK
Stopped pulsing because the TE bit = “0”
Write data to the UiTB register
Tc = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to UiBRG register
i: 0 to 2
Transfer clock
UiC1 register
TE bit
UiC1 register
TI bit
CLKi
TxDi
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
CTSi
“0”
“1”
Stopped pulsing because CTSi = “H”
1 / fEXT
Write dummy data to UiTB register
UiC1 register
TE bit
UiC1 register
TI bit
CLKi
RxDi
UiC1 register
RI bit
RTSi
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
UiC1 register
RE bit
“0”
“1”
Receive data is taken in
Transferred from UiTB register to UARTi transmit register
Read out from UiRB register
fEXT: frequency of external clock
Transferred from UARTi receive register
to UiRB register
SiRIC register
IR bit
“0”
“1”
D0 D1 D2 D3
D4 D5 D6
D7
D0
D1 D2
D3 D4
D5
Transferred from UiTB register to UARTi transmit register
Make sure the following conditions are met when input
to the CLKi pin before receiving data is high:
UiC1 register TE bit = 1 (transmit enabled)
UiC1 register RE bit = 1 (Receive enabled)
Write dummy data to the UiTB register
The above timing diagram applies to the case where the register bits are set as follows:
UiMR register CKDIR bit = 0 (internal clock)
UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
UiRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Cleared to “0” when interrupt request is
accepted, or cleared to “0” in a program
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
as follows:
UiMR register CKDIR bit = 1 (external clock)
UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive
data taken in at the rising edge of the transfer clock)
UiC0 register
TXEPT bit
SiTIC register
IR bit
Even if the reception is completed, the RTS
does not change. The RTS becomes “L”
when the RI bit changes to “0” from “1”.
(1) Example of transmit timing (when internal clock is selected)
(2) Example of receive timing (when external clock is selected)
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