參數(shù)資料
型號: M306H7MC-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù): 38/115頁
文件大?。?/td> 3146K
代理商: M306H7MC-XXXFP
Rev.2.10
Oct 25, 2006
Page 29 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
4. CLOCK GENERATION CIRCUIT
Figure 4.4
PCLKR Register and PM2 Register
Function
Bit symbol
Bit name
Peripheral clock select register (Note)
Symbol
Address
When reset
PCLKR
025E16
000000112
RW
b7
b6
b5
b4
b3
b2
b1
b0
PCLK0
Timers A, B clock select bit
(Clock source for the
timers A and B
0 : f2
1 : f1
00 0
Reserved bit
Must set to
“0”
Note: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
00 0
PCLK1
SI/O clock select bit
(Clock source for UART0
to UART2, SI/O3, SI/O4)
0 : f2SIO
1 : f1SIO
RW
(b7-b2)
Function
Bit symbol
Bit name
Processor mode register 2 (Note 1)
Symbol
Address
After reset
PM2
001E16
XXX000002
RW
b7 b6 b5 b4 b3 b2 b1 b0
00
0
Reserved bit
Must set to “0”
Reserved bit
Must set to “0”
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable).
Note 2: Once this bit is set to “1”, it cannot be cleared to “0” in a program.
Note 3: If the PM21 bit is set to “1,” writing to the following bits has no effect.
CM02 bit of CM0 register
CM05 bit of CM0 register (main clock is not halted)
CM07 bit of CM0 register (CPU clock source does not change)
CM10 bit of CM1 register (stop mode is not entered)
RW
PM21
(b7-b5)
System clock protective
bit
0 : Clock is protected by PRCR
register
1 : Clock modification disabled
(Note 2, Note 3)
(b4-b2)
(b0)
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