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| 型號(hào)： | M306H7MC-XXXFP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 7/115頁(yè) |
| 文件大?。?/td> | 3146K |
| 代理商： | M306H7MC-XXXFP |
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Rev.2.10
Oct 25, 2006
Page 104 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
Table 10.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 10.3 shows
pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 10.4 lists
the P64 pin functions during clock synchronous serial I/O mode. Note that for a period from when the UARTi
operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output
is selected, this pin is in a high-impedance state.)
Table 10.3
Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Table 10.4
P64 Pin Functions
Pin name
Function
Method of selection
TxDi (i = 0 to 2)
(P63, P67, P70)
Serial data output
Serial data input
Transfer clock output
Transfer clock input
I/O port
(Outputs dummy data when performing reception only)
RxDi
(P62, P66, P71)
CLKi
(P61, P65, P72)
UiMR register’s CKDIR bit=0
UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(Can be used as an input port when performing transmission only)
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=0
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1
UiC0 register’s CRD bit=1
CTS input
RTS output
CTSi/RTSi
(P60, P64, P73)
Pin function
Bit set value
U1C0 register
UCON register
PD6 register
CRD
CRS
RCSP
CLKMD1
CLKMD0
PD6_4
P64
1
0
Input: 0, Output: 1
CTS1
0
00
0
RTS1
1
00
CTS0(Note1)
0
CLKS1
0
00
1
0
1(Note 2)
1
Note 1: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0 enabled) and the U0
C0 register’s CRS bit to “1” (RTS0 selected).
Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
High if the U1C0 register’s CLKPOL bit = 0
Low if the U1C0 register’s CLKPOL bit = 1
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