參數(shù)資料
型號： M306H7MC-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 110/115頁
文件大?。?/td> 3146K
代理商： M306H7MC-XXXFP
Rev.2.10
Oct 25, 2006
Page 94 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
Figure 10.1
UARTi Block Diagram
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
Clock source selection
Internal
External
CTS/RTS disabled
CTS/RTS selected
RxD0
1 / (n0+1)
1/16
1/2
U0BRG
register
CLK0
CTS0 / RTS0
f1SIO or f2SIO
f8SIO
f32SIO
RTS0
CTS0
TxD0
(UART0)
f1SIO or f2SIO
1/2
1/8
f8SIO
1/4
f32SIO
f1SIO
f2SIO
PCLK1=0
PCLK1=1
CLK1 to CLK0
002
012
102
CKDIR=0
CKDIR=1
CKPOL
CKDIR=0
CKDIR=1
CRS=1
CRS=0
CRD=0
CRD=1
RCSP=0
RCSP=1
“H”
CRD=0
CRD=1
RxD polarity
reversing circuit
Main clock
UART reception
Clock synchronous
type
UART transmission
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
Receive
clock
Transmit
clock
Reception
control circuit
Transmission control
circuit
Transmit/
receive
unit
TxD
polarity
reversing
circuit
CLK
polarity
reversing
circuit
CTS/RTS disabled
CTS0 from UART1
UART reception
Clock synchronous
type
RxD1
TxD1
(UART1)
1 / (n1+1)
1/16
1/2
U1BRG
register
CLK1
f1SIO or f2SIO
f8SIO
f32SIO
CLK1 to CLK0
002
012
102
CKDIR=0
CKDIR=1
CKPOL
CKDIR=0
CKDIR=1
CRD=0
CRD=1
CLKMD0=0
CLKMD1=0
CRS=1
CRS=0
RCSP=0
RCSP=1
CLKMD0=1
CLKMD1=1
RxD polarity
reversing circuit
Clock source selection
Internal
External
UART transmission
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
Receive
clock
Transmit
clock
Reception
control circuit
Transmission
control circuit
Transmit/
receive
unit
TxD
polarity
reversing
circuit
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CLK
polarity
reversing
circuit
RTS1
CTS1
Clock output
pin select
CTS/RTS disabled
CTS/RTS selected
CTS0 from UART0
CTS1 / RTS1/
CTS0/ CLKS1
Note: UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.
i = 0 to 2
ni: Values set to the UiBRG register
SMD2 to SMD0, CKDIR: UiMR register's bits
CLK1 to CLK0, CKPOL, CRD, CRS: UiC0 register's bits
CLKMD0, CLKMD1, RCSP: UCON register's bits
RxD2
CLK2
CTS2 / RTS2
RTS2
CTS2
TxD2
(UART2)
1 / (n2+1)
1/16
1/2
U2BRG
register
f1SIO or f2SIO
f8SIO
f32SIO
CLK1 to CLK0
002
012
102
CKDIR=0
CKDIR=1
CKPOL
CKDIR=0
CKDIR=1
CRS=1
CRS=0
CRD=0
CRD=1
Reception
control circuit
Transmission
control circuit
UART reception
Clock synchronous
type
UART transmission
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
Receive
clock
Transmit
clock
RxD polarity
reversing circuit
Internal
External
Clock source selection
TxD
polarity
reversing
circuit
Transmit/
receive
unit
(Note)
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
CLK
polarity
reversing
circuit
CTS/RTS disabled
CTS/RTS
selected
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