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參數(shù)資料
| 型號(hào)： | M306H7MC-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 75/115頁(yè) |
| 文件大?。?/td> | 3146K |
| 代理商： | M306H7MC-XXXFP |
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Rev.2.10
Oct 25, 2006
Page 62 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
8. DMAC
8.
DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from
the source address to the destination address. The DMAC uses the same data bus as used by the CPU. Because the
DMAC has higher priority of bus control than the CPU and because it makes use of a cycle steal method, it can transfer
one word (16 bits) or one byte (8 bits) of data within a very short time after a DMA request is generated. Figure 8.1
shows the block diagram of the DMAC.
Table 8.1 shows the DMAC specifications. Figures 8.2 to 8.4 show the DMAC-related registers.
Figure 8.1
DMAC Block Diagram
A DMA request is generated by a write to the DMiSL register (i = 0 to 1)’s DSR bit, as well as by an interrupt request
which is generated by any function specified by the DMiSL register’s DMS and DSEL3 to DSEL0 bits. However,
unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the interrupt control register, so
that even when interrupt requests are disabled and no interrupt request can be accepted, DMA requests are always
accepted. Furthermore, because the DMAC does not affect interrupts, the interrupt control register’s IR bit does not
change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMiCON register’s DMAE bit = “1”
(DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA transfer cycle, the
number of transfer requests generated and the number of times data is transferred may not match. For details, refer to
“DMA Requests”.
Data bus low-order bits
DMA latch high-order bits
DMA latch low-order bits
DMA0 source pointer SAR0(20)
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20) (Note)
Data bus high-order bits
Address bus
DMA1 destination pointer DAR1 (20)
DMA1 source pointer SAR1 (20)
DMA1 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 transfer counter TCR1 (16)
(addresses 002916, 002816)
(addresses 003916, 003816)
(addresses 002216 to 002016)
(addresses 002616 to 002416)
(addresses 003216 to 003016)
(addresses 003616 to 003416)
Note: Pointer is incremented by a DMA request.
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| M306H7MG-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER |
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