參數(shù)資料
型號(hào)： M306H7MC-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù)： 106/115頁(yè)
文件大?。?/td> 3146K
代理商： M306H7MC-XXXFP
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Rev.2.10
Oct 25, 2006
Page 90 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
9.TIMERS
9.2.2
Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of other
timers (see Table 9.7) . Figure 9.18 shows TBiMR register in event counter mode.
Table 9.7
Specifications in Event Counter Mode
Figure 9.18
TBiMR Register in Event Counter Mode
Item
Specification
Count source
External signals input to TBiIN pin (i=0 to 5) (effective edge can be selected
in program)
Timer Bj overflow or underflow (j=i-1, except j=2 if i=0, j=5 if i=3)
Count operation
Down-count
When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1)
n: set value of TBi register
000016 to FFFF16
Count start condition
Set TBiS bit1 to “1” (= start counting)
Count stop condition
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
Count source input
Read from timer
Count value can be read by reading TBi register
Write to timer
When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Notes:
1. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i=0 to 5)
TB0MR to TB2MR
039B16 to 039D16
00XX00002
TB3MR to TB5MR
035B16 to 035D16
00XX00002
Bit name
Function
Bit symbol
RW
b7
b6
b5
b4
b3
b2
b1
b0
Operation mode select bit
0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0
Count polarity select
bit (Note 1)
MR2
MR1
MR3
TCK1
TCK0
01
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Must not be set
b3 b2
Note 1: Effective when the TCK1 bit = “0” (input from TBiIN pin). If the TCK1 bit = “1” (TBj overflow or underflow), these
bits can be set to “0” or “1”.
Note 2: The port direction bit for the TBiIN pin must be set to “0” (= input mode).
Has no effect in event counter mode.
Can be set to “0” or “1”.
Event clock select
0 : Input from TBiIN pin (Note 2)
1 : TBj overflow or underflow
(j = i – 1, except j = 2 if i = 0,
j = 5 if i = 3)
RW
RO
TB0MR, TB3MR registers
Must be set to “0” in event count mode
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
When write in event counter mode, set to “0”. When read in event
counter mode, its content is indeterminate.
Address
After reset
Symbol
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