
Universal Serial Bus
93
Specifications in this manual are tentative and subject to change
Rev. E
MITSUBISHI MICROCOMPUTERS
M30245 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
USB Endpoint x OUT CSR (x = 1 to 4)
The USB Endpoint x OUT CSR (Control and Status Register), shown in Figure 1.61, contains control and
status information for the respective OUT EP 1-4.
OUTxCSR0 (OUT_BUF_STS0) and OUTxCSR1 (OUT_BUF_STS1):
Two status flags, indicate the current status of the OUT buffer. The buffer status flags are updated when
one of the following events occurs:
1. The USB FCU successfully receives a data set from the host.
2. The CPU unloads a data set from the buffer (writes a “1” to CLR_OUT_BUF_RDY).
3. The CPU writes a “1” to the FLUSH bit.
OUTxCSR2 (OVER_RUN):
A status flag, “1” indicates an over run has occurred in an isochronous data transfer. The USB FCU
updates this flag to a “1” at the beginning of an OUT token when two data packets are already present in
the buffer.
OUTxCSR3 (FORCE_STALL):
A status flag, “1” indicates that the USB FCU detected a Packet size larger than MAXP violation. The
USB FCU returns a STALL as a handshake packet for the current transaction.
OUTxCSR4 (DATA_ERR):
A status flag, “1” indicates a data error (bit stuffing or CRC error) has occurred in an OUT isochronous
data packet.
OUTxCSR5 (CLR_OUT_BUF_RDY):
The CPU writes a “1” to this bit after unloading a data set from the buffer. The CPU can only unload data
from the buffer and set this bit when OUTxCSR1 (OUT_BUF_STS1) is a “1”.
OUTxCSR6 (CLR_OVER_RUN):
The CPU writes a “1” to this bit to clear the OVER_RUN status flag.
OUTxCSR7 (CLR_FORCE_STALL):
The CPU writes a “1” to this bit to clear the FORCE_STALL status flag.
OUTxCSR8 (CLR_DATA_ERR):
The CPU writes a “1” to this bit to clear the DATA_ERR status flag.
OUTxCSR9 (TOGGLE_INIT):
The CPU writes a “1” to this bit to initialize the data sequence, and force the next packet’s data PID to a
DATA0 for reception.
OUTxCSR10 (FLUSH):
The CPU writes a “1” to this bit to flush the OUT buffer. This bit must only be set to a “1” when the
OUT_BUF_STS1 flag is a “1”.
When there is one data set in the OUT buffer, a flush causes the OUT buffer to be empty.
When there are two data sets in the OUT buffer, a flush causes the older packet to be flushed from the
OUT buffer.
The USB FCU updates the buffer status flags the same way as a data set is unloaded from the host
when it sees a FLUSH. Setting the FLUSH bit during reception could produce unpredictable results.