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| 型號(hào)： | M30245MC-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 232/244頁(yè) |
| 文件大小： | 3535K |
| 代理商： | M30245MC-XXXGP |
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Universal Serial Bus
Specifications in this manual are tentative and subject to change
Rev. E
MITSUBISHI MICROCOMPUTERS
M30245 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
88
EP0CSR5 (SETUP_END):
A status flag, “1” indicates a premature completion of a control transfer when one of the following
events occurs:
A control transfer ends before the specific length of data is transferred during the data phase (status
phase starts before DATA_END bit is set)
A new SETUP is received before successfully completing the status phase of the previous control
transfer.
EP0CSR6 (CLR_OUT_BUF_RDY):
The CPU writes a “1” to this bit after unloading a data set from the buffer. Writing a “1” to this bit clears
the OUT_BUF_RDY status flag.
EP0CSR7 (SET_IN_BUF_RDY):
The CPU writes a “1” to this bit after loading a data set to the buffer. Writing a “1” to this bit sets the
IN_BUF_RDY status flag.
EP0CSR8 (CLR_SETUP):
The CPU writes a “1” to this bit to clear the SETUP status flag.
EP0CSR9 (SET_DATA_END):
The CPU writes a “1” to this bit when it writes (IN data phase) the last data packet to the buffer or reads
(OUT data phase) the last data packet from the buffer. The CPU sets this bit at the same time (using the
same instruction) as it sets the CLR_OUT_BUF_RDY bit or sets the SET_IN_BUF_RDY bit for the last
data set. Writing a “1” to this bit sets the DATA_END status flag.
EP0CSR10 (CLR_FORCE_STALL):
The CPU writes a “1” to this bit to clear the FORCE_STALL status flag.
EP0CSR11 (CLR_SETUP_END):
The CPU writes a “1” to this bit to clear the SETUP_END status flag.
EP0CSR12 (SEND_STALL):
The CPU writes a “1” to this bit when it decodes an invalid or unsupported request from the host. The
CPU should only write a “1” to this bit at the same time it writes a “1” to EP0CSR6
(CLR_OUT_BUF_RDY). When this bit is a “1”, the USB FCU returns STALL handshakes for all subse-
quent IN/OUT transactions. The CPU writes a “0” to clear it after it receives a new SETUP packet. It is up
to the firmware to decide what SETUP packet should lead the clearing of the SEND_STALL bit.
EP0CSR13 (DATA_END_MASK):
This bit is for the CPU to mask or unmask the clearing of DATA_END as an EP0 interrupt source –
default is masked (clearing of DATA_END does not cause an EP0 interrupt).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M30245FCGP | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100 |
| M30621FCAGP | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP80 |
| M30625MGM-XXXGP | 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80 |
| M30621MCM-XXXGP | 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80 |
| M30621FCMGP | 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP80 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30245MG | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245MGGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245MG-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245MG-XXXGF | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245MG-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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