Frequency Synthesizer Circuit
47
Specifications in this manual are tentative and subject to change
Rev. E
MITSUBISHI MICROCOMPUTERS
M30245 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Frequency synthesizer circuit
The frequency synthesizer circuit generates a 48MHz clock (fUSB) needed by the USB block and a clock fSYN that
are a multiple of the external input reference clock f(XIN). A block diagram of the circuit is shown in Figure 1.23.
Figure 1.23. Frequency Synthesizer Circuit
The frequency synthesizer consists of a prescaler, frequency multiplier, a frequency divider, and five registers:
FSP; FSM; FSC; FSD; and FSCCR. Clock f(XIN) is prescaled down using FSP to generate fPIN. fPIN is multiplied by
FSM to generate an fVCO clock, which is then divided by FSD to produce the clock fSYN. The fVCO clock is
optimized for 48 MHz operation and is buffered and sent out of the frequency synthesizer block as signal fUSB.
This signal is used by the USB block.
The FSC0 bit in the FSC Control Register enables the frequency synthesizer block. When disabled (FSC0 = “0”),
fVCO is held at either a high or low state. When the frequency synthesizer control bit is active (FSC0 = “1”), a lock
status (LS = “1”) indicates that fSYN and fVCO are the correct frequency. The LS and FSCO control bits in the FSC
Control register are shown in Figure 1.24.
When using the frequency synthesizer, a low-pass filter must be connected to the LPF pin. Once the frequency
synthesizer is enabled, a delay of 2-5ms is recommended before the output of the frequency synthesizer is used.
This is done to allow the output to stabilize. It is also recommended that none of the registers be modified once the
frequency synthesizer is enabled as it will cause the output to be temporarily (2-5ms) unstable.
The MCU clock source is selected via the Frequency Synthesizer Clock Control register (FSCCR). See Figure
1.25.
Note: None of the registers must be written to once the frequency synthesizer is enabled and used as the
system clock source (FSCCR register, address 03DB16, bit ‘0’ set to ‘1’) because it will cause the output
of the PLL to freeze. Switch system back to f(XIN) and disable before modifying PLL registers.
FSP
Data Bus
FSM
FSC
FSD
03DE
03DD
03DC
03DF
Frequency
Multiplier
Frequency
Divider
8
B
it
LS
8 Bit
f(Xin)
fVCO
fSYN
fUSB
Prescaler
8
B
it
fPIN
FSCCR
FSCCR0
03DB
EN
USBC5