Universal Serial Bus
71
Specifications in this manual are tentative and subject to change
Rev. E
MITSUBISHI MICROCOMPUTERS
M30245 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The USB Function Interrupt has multiple interrupt sources that can be enabled within the USB Function
Interrupt Enable Register (USBIE).
EP0 Interrupt
The EP0 interrupt is generated when one of the following events occur:
A data set is successfully received
A data set is successfully sent
EP0CSR3 (DATA_END) flag is cleared. This event is maskable and the default is masked.
A control transfer ends prematurely (i.e., the USB FCU sets the SETUP_END bit). See USB programming
note #1.
USB Function Interrupt
The USB Function interrupt can be triggered by:
The interrupts from eight endpoints (EP1-EP4 IN/OUT). The interrupts indicate if a data set was either sent
or received.
A data flow error from any of the nine endpoints (including EP0)
The enabling of any IN endpoint (EP1-EP4 IN).
The corruption of the final ACK of a Control Read transfer's Data Stage. See USB programming Note #2.
Each endpoint interrupt is enabled by setting the corresponding bit in the USB Interrupt Enable register
(USBIE).
Interrupt status flags associated with each source are contained in USB Interrupt Status register (USBIS).
USB Reset Interrupt
A USB Reset Interrupt is generated when the USB Function Control Unit (USB FCU) sees a SE0 present on
D+/D- for at least 2.5us. When a reset signal is detected by the USB FCU, an internal reset pulse is also
generated to reset all USB internal registers to the default values.
When the CPU recognizes a USB Reset Interrupt, it re-initializes the USB FCU to ensure that the USB
operation functions properly.
The USB Reset Interrupt Control register (RSTIC) contains the USB Reset Interrupt request bit and interrupt
priority select bits used to enable the interrupt and set the software priority level.
USB Resume Interrupt
A USB Resume Interrupt is generated when the USB FCU is in the suspend state and detects non-idle
signaling on the D+/D-.
The USB Resume Interrupt Control register (RSMIC) contains the USB Resume Interrupt request bit and
interrupt priority select bits used to enable the interrupt and set its software priority level.
USB SOF Interrupt
The USB SOF (Start-Of-Frame) Interrupt is used to control the transfer of isochronous data. The USB FCU
generates a USB SOF Interrupt request when a start-of-frame packet is received.
Because the start-of-frame packet could be corrupted, a new frame might start without successful reception
of the SOF packet. For this reason, an artificial SOF is provided. The frame timer signals a time out when a
SOF packet is not received within the allotted time. The device generates an SOF interrupt once every
frame. Setting bit 2 of the USB ISO Control Register to a “1” enables the artificial SOF function.
Register SOFIC contains the USB SOF Interrupt’s request bit and interrupt priority select bits that are used
to enable the interrupt and set its software priority level.