Clock Generating Circuit
Specifications in this manual are tentative and subject to change
Rev. E
MITSUBISHI MICROCOMPUTERS
M30245 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
40
Clock Control
Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, this clock is divided by 8 to
produce the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616).
Stopping the clock, after switching the operating clock source of CPU to the subclock, reduces the power
dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces power dissipation. This bit changes
to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from
low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Subclock
The subclock is generated by the subclock oscillation circuit. No subclock is generated after a reset. After
oscillation is started using the port Xc select bit (bit 4 at address 000616), the subclock can be selected as
the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the subclock
oscillation has fully stabilized before switching.
After the oscillation of the subclock oscillation circuit has stabilized, the drive capacity of the subclock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the subclock oscillation circuit reduces the power dissipation. This bit
changes to “1” when changing to stop mode and at a reset.
BCLK
The BCLK is the clock that drives the CPU, and is equal to fc or the clock that is derived by dividing the
main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK
signal can be output from the BCLK pin (P53) by use of the BCLK output disable bit (bit 7 at address
000416) in the memory expansion and the microprocessor modes.
The main clock division select bit 0 (bit 6 at address 000616) changes to “1” when shifting from high-speed/
medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to
stop mode, the value before stop mode is retained.
Peripheral function clock (f1, f8, f32, f1SIO2, f8SIO2, f32SIO2, fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
fc32
This clock is derived by dividing the subclock by 32. It is used for the Timer A counts.
fc
This clock has the same frequency as the subclock. It is used for the BCLK and for the watchdog timer.
fUSB
This clock provides a 48 MHz signal required for USB operation. It is derived from the Frequency Synthesizer
circuit.