
Universal Serial Bus
79
Specifications in this manual are tentative and subject to change
Rev. E
MITSUBISHI MICROCOMPUTERS
M30245 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
OUT Endpoint FIFO Flush
A software flush causes the USB FCU to act as if a data set has been unloaded from the buffer. The user
must only set the flush bit when OUT_BUF_STS1 = 1, which indicates that one or two data sets have
been received. When there is one data set in the buffer, a flush causes the buffer to empty. When there
are two data sets in the buffer, a flush causes the older data set to be flushed out from the buffer. A flush
also updates the buffer status flags of the corresponding EPx OUT CSR.
The status of Endpoint 1-4 OUT buffers can be obtained from the two status bits of the EPx OUT CSR of
the corresponding endpoint as shown in Table 1.36.
OUT_BUF_STS1
OUT_BUF_STS0
Buffer Status
0
No data set in the OUT buffer
01
Single buffer mode:
N/A
Double buffer mode:
N/A
10
Single buffer mode:
N/A
Double buffer mode:
One data set in the OUT buffer
11
Single buffer mode:
One data set in the OUT buffer
Double buffer mode:
Two data sets in the OUT buffer
Table 1.36. Endpoints 1-4 OUT buffer status
Interrupt Endpoints
Any endpoint can be used for interrupt transfers. For normal interrupt transfers, the interrupt transactions
behave the same as bulk transactions, i.e., no special setting is required.
The IN endpoints may be used to communicate rate feedback information for certain types of isochronous
functions. Setting the INTPT bit in the IN CSR register of the corresponding IN CSR enables this function.
When the INTPT bit is set, the data toggle bit changes after each packet is sent regardless of the presence
or type of handshake that is returned from the host.
The operation sequence for an IN endpoint used to communicate rate feedback information is listed in the
following steps.
1. Set single buffer mode for the endpoint in use;
2. Set INTPT bit of the IN CSR;
3. Load interrupt status information and set SET_IN_BUF_RDY bit in the IN CSR;
4. Repeat step 3 for all subsequent interrupt status updates.
When an interrupt endpoint is used for rate feedback, the device always has data to send back to the host,
even if the data conveys that everything is ‘fine’. Therefore, the device never NAKs an IN token from the
host. The device always sends out the data in the FIFO in response to an IN token regardless of the IN
buffer status bits.