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| 型號(hào)： | M30222FGGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 43/236頁(yè) |
| 文件大小： | 1955K |
| 代理商： | M30222FGGP |
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1-138
Under
development
Specifications in this manual are tentative and subject to change
Rev. H
UART2 in SPI mode
MITSUBISHI MICROCOMPUTERS
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The SPI functionality is an 8 bit, synchronous communication protocol that is user programmable to
use one of four different transfer formats. The four transfer formats support the four combinations of
clock phase and clock polarity, as the clock relates to the data. Figure 1.110 shows the SPI system
level view.
The existing UART2 already provides two of the transfer formats, with the CKPOL control bit. The SPI
mode adds the ability to change the phase of the clock, with respect to the transmitted data, in each of
the two existing clock polarity formats.
UART2 in SPI mode
The UART2 special mode register 3 (address 037516) is used to activate the SPI mode.
Figure 1.109 shows the UART2 special mode register 3.
Fig. 1.109. UART2 Special mode register 3
Symbol
Address
When reset
U2SMR3
037516
0016
UART2 Special mode register 3 (I2C and SPI bus exclusive use register)
DL0
DL1
DL2
0 : Normal mode
1 : SPI mode
Bit name
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
SPIM
CPHA
SPI mode select bit
0 0 0 : Analog delay is selected
0 0 1 : 2 cycle of 1/f(X IN)
0 1 0 : 3 cycle of 1/f(X IN)
0 1 1 : 4 cycle of 1/f(X IN)
1 0 0 : 5 cycle of 1/f(X IN)
1 0 1 : 6 cycle of 1/f(X IN)
1 1 0 : 7 cycle of 1/f(X IN)
1 1 1 : 8 cycle of 1/f(X IN)
b7 b6 b5
W
R
SPI clock-phase
select bit
Function during clock
synchronous serial I/O mode
Function during
UART mode
0 : Data latched on
falling clock edge
1 : Data latched on
rising clock edge
Must always be "0'
Digital delay
is selected
SDA digital delay
set up bit (Note
1, 2, 3, 4, 5)
Nothing is assigned. In an attempt to write to these bits, write "0". When read the
value is indeterminate. However, when SDDS = "1", a "0" value is read.
_ _
Note 1:
This bit can be read or written to when UART2 special mode register U2SMR at address 037716 bit 7
(SDDS: SDA digital delay select bit) = "1". When the initial value of UART2 special mode register 3
(U2SMR3 is read after setting SDDS = "1", the value is "0016". When writing to U2SMR3 after setting
SDDS = "1", be sure to write 0s to bits 0 - 4. When SDDS = "0", This register cannot be written to;
when read, the value is indeterminate.
Note 2:
These bits are initialized to "000" when SDDS = "0", with the analog delay circuit selected. After a reset
these bits are set to "000", with the analog delay circuit selected. However, because these bits can be read
only when SDDS = "1", the value read from these bits when SDDS = "0" is indeterminate.
Note 3:
When analog delay is selected, only the analog delay value is effective; when digital delay is selected,
only the digital delay value is effective.
Note 4:
The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock,
the amount of delay increases by about 100ns. Be sure to take this into account when using this device.
Note 5:
Reset values for SPIM and CPHA are not affected by the state of SDDs. Their reset values are always "0".
(Note 1)
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| M30222FGFP | 16-BIT, FLASH, MICROCONTROLLER, PQFP100 |
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| M30240M6-XXXFP | 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80 |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| M30222FG-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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