
1-132
Under
development
Specifications in this manual are tentative and subject to change
Rev. H
UART2 in I2C Mode
MITSUBISHI MICROCOMPUTERS
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.105 shows the functional block diagram for I2C mode. Setting “1” in the I2C mode select bit
(IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock
input-output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission
output, so the SDA output changes after SCL fully goes to “L”. The SDA digital delay select bit (bit 7
at address 037716) can be used to select between analog delay and digital delay. When digital delay
is selected, the amount of delay can be selected in the range of 2 cycles to 8 cycles of f1 using UART2
special mode register 3 (at address 037516). Delay circuit select conditions are shown in Table 1.42.
Table 1.42. Delay circuit select conditions
Fig. 1.105. Functional block diagram for I2C mode
P70 through P72 conforming to the simplified I C bus
Selector
I/O
Timer
delay
Noise
Filter
Timer
UART2
Selector
(Port P71 output data latch)
I/O
P70/TxD2/SDA
P71/RxD2/SCL
Reception register
CLK
Internal clock
UART2
External clock
Selector
UART2
I/O
Timer
P72/CLK2
Arbitration
Start condition detection
Stop condition detection
Data bus
Falling edge
detection
D
T
Q
D
T
Q
D
T
Q
NACK
ACK
UART2
R
UART2 transmission/
NACK interrupt
request
UART2 reception/ACK
interrupt request
DMA1 request
9th pulse
IICM=1
IICM=0
IICM=1
IICM=0
IICM=1
IICM=0
IICM=1
IICM=0
IICM=1
IICM=0
Port reading
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P71 of the direction register.
L-synchronous
output enabling bit
S
R Q
Bus busy
IICM=1
IICM=0
Bus collision/start, stop
condition detection
interrupt request
Bus collision
detection
Noise
Filter
Transmission
register
To DMA0, DMA1
Q
Noise
Filter
To DMA0
2
SDDS = "0" or DL = "000"
Digital delay is selected
Analog delay is selected
No delay
1
0
1
0
001
to
111
000
(000)
When digital delay is selected,no analog
delay is added. Only digital delay is effective
When DL is set ot "000", analog delay is
selected no matter what value is set in SDDS.
When SDDS is set to "0", DL is initialized, so
that DL = "000".
When IICM = "0", no delay circuit is selected.
Always made sure SDDS = "0".
Register value
IICM SDDS
DL
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