參數(shù)資料
型號(hào)： M30222FGGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 164/236頁(yè)
文件大?。?/td> 1955K
代理商： M30222FGGP
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1-34
Under
development
Specifications in this manual are tentative and subject to change
Rev. H
Power Control
MITSUBISHI MICROCOMPUTERS
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 1.19. State Transition diagram of power control mode
All oscillators stopped
Stop Mode
Medium-speed mode
(divided-by-8 mode)
RESET
Normal Mode
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
CM10 = "1"
Interrupt
State Transitions for Stop and Wait modes
Main clock is oscillating
Sub clock is stopped
Medium-speed mode
(divided-by-8 mode)
BCLK : f(Xin )/8
CM07 = "0" CM06 = "1"
High-speed mode
BCLK ; f(Xin )
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "0"
Medium-speed mode
(divided-by-4 mode)
BCLK : f(Xin )/4
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "0"
BCLK ; f(Xin )/2
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "1"
Medium-speed mode
(divided-by-2 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(Xin )/4
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "1"
Medium-speed mode
(divided-by-8 mode)
BCLK : f(Xin )/8
CM07 = "0"
CM06 = "1"
High-speed mode
BCLK ; f(Xin )
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "0"
Medium-speed mode
(divided-by-4 mode)
BCLK : f(Xin )/4
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "0"
BCLK ; f(Xin )/2
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "1"
Medium-speed mode
(divided-by-2 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(Xin )/4
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "1"
CM04 = "0"
Main clock is oscillating
Sub clock is stopped
CM04 = "1"
Main clock is oscillating
Sub clock is oscillating
CM06 = "0"
(Notes 1, 3)
CM07 = "0" (Note 1)
CM06 = "0" (Note 3)
CM04 = "1"
CM07 = "1" (Note 2)
CM05 = "1"
CM05 = "0"
CM04 = "1" (Notes 1, 3)
CM04 = "0"
CM06 = "1"
CM07 = "0"
(Note 1, 3)
CM07 = "1"
(Note 2)
CM07 = "0" (Note 1)
CM06 = "1"
CM04 = "0"
All oscillators stopped
Stop Mode
All oscillators stopped
Stop Mode
High speed /
Medium-speed mode
Low-speed / Low power
dissipation mode
CPU operation stopped
Wait mode
CPU operation stopped
Wait mode
CPU operation stopped
Wait mode
CM10 ="1"
WAIT
instruction
Interrupt
Main clock is oscillating
Sub clock is oscillating
Low-speed mode
BCLK : f(Xcin)
CM07 = "1"
BCLK : f(Xcin)
CM07 = "1"
Main clock is stopped
Sub clock is oscillating
Low-power dissipation mode
CM05 = "1"
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
State Transitions for normal mode
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