
1-41
Under
development
Specifications in this manual are tentative and subject to change
Rev. H
Overview of Interrupts
MITSUBISHI MICROCOMPUTERS
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level
selection bits, or processor interrupt priority level (IPL). Whether an interrupt request is present or
absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level
selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable
flag (I flag) and the IPL are located in the CPU flag register (FLG). Figure 1.23 shows the memory map
of the interrupt control registers.
Figure 1.23. Memory map of the interrupt control registers.
Symbol
Address
When reset
INTiIC(i=0 to 1)
005D16 , 005E16
XX000000 2
INT2IC/SI3IC
005F16
XX000000 2
INT31C/SI4IC
004416
XX000000 2
INT4IC/TA3IC
005816
XX000000 2
INT5/TA4IC
005916
XX000000 2
INTiIC(i= 6 to 7)
004916, 004816
XX000000 2
Bit name
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
ILVL0
IR
POL
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
Always set to “0”
ILVL1
ILVL2
Note 1 To rewrite the interrupt control register, do so at a point that does not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Note 2: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
(Note 2)
Interrupt control register
b7
b6
b5
b4
b3
b2
b1
b0
Bit name
Function
Bit symbol
W
R
Symbol
Address
When reset
TBiIC(i=3 to 5)
0045 16 to 004716
XXXX0000 2
BCNIC
004A16
XXXX0000 2
DMiIC(i=0, 1)
004B16, 004C16
XXXX0000 2
KUPIC
004D16
XXXX0000 2
ADIC
004E16
XXXX0000 2
SiTIC(i=0 to 2)
0051 16 005316, 004F16
XXXX0000 2
SiRIC(i=0 to 2)
0052 16, 005416, 005016
XXXX0000 2
TAiIC(i=0 to 2)
0055 16 to 005716
XXXX0000 2
TBiIC(i=0 to 2)
005A 16 to 005C16
XXXX0000 2
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
(Note 1)
Note 1: To rewrite the interrupt control register, do so at a point that does not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Note 2: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
(Note 2)
0: Selects falling edge
Selects rising edge
1:
Nothing is assigned.
Write "0" when writing to these bits. If read, the value is "0".
Nothing is assigned.
Write "0" when writing to these bits. If read, the value is "0".