
1-113
Under
development
Specifications in this manual are tentative and subject to change
Rev. H
Serial Communications
MITSUBISHI MICROCOMPUTERS
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 1.86. Serial I/O-related registers (6)
Symbol
Address
When reset
U2SMR3
037516
0016
UART2 Special mode register 3 (I2C and SPI bus exclusive use register)
DL0
DL1
DL2
0 : Normal mode
1 : SPI mode
Bit name
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
SPIM
CPHA
SPI mode select bit
0 0 0 : Analog delay is selected
0 0 1 : 2 cycle of 1/f(X IN)
0 1 0 : 3 cycle of 1/f(X IN)
0 1 1 : 4 cycle of 1/f(X IN)
1 0 0 : 5 cycle of 1/f(X IN)
1 0 1 : 6 cycle of 1/f(X IN)
1 1 0 : 7 cycle of 1/f(X IN)
1 1 1 : 8 cycle of 1/f(X IN)
b7 b6 b5
W
R
SPI clock-phase
select bit
Function during clock
synchronous serial I/O mode
Function during
UART mode
0 : Data latched on
falling clock edge
1 : Data latched on
rising clock edge
Must always be "0'
Digital delay
is selected
SDA digital delay
set up bit (Notes
1, 2, 3, 4, 5)
Nothing is assigned. Write "0" when writing to these bits. If read, the value is
Indeterminate. However, when SDDS = "1", a "0" value is read.
_ _
UART2 special mode register 2
Symbol
Address
When reset
U2SMR2
037616
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol
W
R
Function
STAC
SWC2
SDHI
I C mode selection bit 2
SCL wait output bit
0 : Disabled
1 : Enabled
SDA output stop bit
UART2 initialization bit
Clock-synchronous bit
Refer to Table 1.44
0 : Disabled
1 : Enabled
IICM2
CSC
SWC
ASL
0 : Disabled
1 : Enabled
SDA output disable bit
SCL wait output bit 2
0: Enabled
1: Disabled (high impedance)
0 : Disabled
1 : Enabled
0: UART2 clock
1: 0 output
2
SHTC
Start/stop condition
control bit
Set this bit to "1" in I 2C mode
Note 1:
This bit can be read or written to when UART2 special mode register U2SMR at address 037716 bit 7
(SDDS: SDA digital delay select bit) = "1". When the initial value of UART2 special mode register 3
(U2SMR3 is read after setting SDDS = "1", the value is "0016". When writing to U2SMR3 after setting
SDDS = "1", be sure to write 0s to bits 0 - 4. When SDDS = "0", This register cannot be written to;
when read, the value is indeterminate.
Note 2:
These bits are initialized to "000" when SDDS = "0", with the analog delay circuit selected. After a reset
these bits are set to "000", with the analog delay circuit selected. However, because these bits can be read
only when SDDS = "1", the value read from these bits when SDDS = "0" is indeterminate.
Note 3:
When analog delay is selected, only the analog delay value is effective; when digital delay is selected,
only the digital delay value is effective.
Note 4:
The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock,
the amount of delay increases by about 100ns. Be sure to take this into account when using this device.
Note 5:
Reset values for SPIM and CPHA are not affected by the state of SDDs. Their reset values are always "0".
(Note 1)