
1-133
Under
development
Specifications in this manual are tentative and subject to change
Rev. H
UART2 in I2C Mode
MITSUBISHI MICROCOMPUTERS
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
An attempt to read Port P71 (SCL) gets the pin's level regardless of the content of the port direction
register. The initial value of SDA transmission output in this mode goes to the value set in port P70.
The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and of
UART2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-
detection interrupt, and acknowledgment detection interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the
SDA terminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection
interrupt refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected
with the SCL terminal (P71) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register)
is set to “1” by the start condition detection, and set to “0” by the stop condition detection.
The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal
level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment
detection interrupt refers to the interrupt that occurs when SDA terminal’s level is detected already
went to “L” at the 9th transmission clock. Also, assigning 1 1 0 1 (UART2 reception) to the DMA1
request factor select bits provides the means to start up the DMA transfer by the effect of acknowledg-
ment detection.
Bit 1 of the UART2 special mode register (037716) is used as the arbitration loss detecting flag control
bit. Arbitration means the act of detecting the nonconformity between transmission data and SDA
terminal data at the timing of the SCL rising edge. This detecting flag is located at bit 3 of the UART2
reception buffer register (037F16), and “1” is set in this flag when nonconformity is detected. Use the
arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte
by byte. When setting this bit to “1” and updated the flag byte by byte if nonconformity is detected, the
arbitration lost detecting flag is set to “1” at the falling edge of the 9th transmission clock.
If update the flag byte by byte, must judge and clear (“0”) the arbitration lost detecting flag after
completing the first byte acknowledge detect and before starting the next one byte transmission.
Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit.
Setting this bit to “1” goes the P71 data register to “0” in synchronization with the SCL terminal level
going to “L”.
Some other functions added are explained here. Figure 1.106 shows their workings.
Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit.
The bus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the
nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit
is set to “0”. If this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer
A0 rather than at the rising edge of the transfer clock.