
1-127
Under
development
Specifications in this manual are tentative and subject to change
Rev. H
Clock Asynchronous Serial I/O Mode
MITSUBISHI MICROCOMPUTERS
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some
extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table
1.40 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface).
Figure 1.100 shows a typical transmit/receive timing in UART mode (compliant with the SIM interface).
Item
Specification
Transfer data format
Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”)
One stop bit (bit 4 of address 0378 16 = “0”)
With the direct format chosen
Set parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 037D16 = “0”).
Set transfer format to LSB (bit 7 of address 037C16 = “0”).
With the inverse format chosen
Set parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 037D16 = “1”)
Set transfer format to MSB (bit 7 of address 037C16 = “1”)
Transfer clock
Withtheinternal clock chosen(bit 3of address 037816= “0”) : fi / 16(n+ 1) (Note1) : fi=f1,f8,f32
(Do not use external clock)
Transmit/receive control
Disable the CTS and RTS function (bit 4 of address 037C16 = “1”)
Other settings
The sleep mode select function is not available for UART2
Set transmissioninterrupt factor to “transmissioncompleted”(bit 4 of address 037D16= “1”)
Transmit start condition
To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 037D16) = “1”
- Transmit buffer empty flag (bit 1 of address 037D16) = “0”
Receive start condition
To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 037D16) = “1”
- Detection of a start bit
When transmitting
When data transmission from the UART2 transfer register is completed
(bit 4 of address 037D16 = “1”)
When receiving
When data transfer from the UART2 receive register to the UART2 receive
buffer register is completed
Error detection
Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)
Framing error (see the specifications of clock-asynchronous serial I/O)
Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the TXD2pin by use of the parity error
signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected
- On the transmission side, a parity error is detected by the level of input to
the RXD2 pin when a transmission interrupt occurs
The error sum flag (see the specifications of clock-asynchronous serial I/O)
Interrupt request
generation timing
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: If an overrun error occurs, the UART2 receive buffer will have the last or most recent data written.
Note also
the UARTi receive interrupt request bit is not set to "1".
Table 1.40. Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)