參數(shù)資料
型號: M29W640GB70ZA6F
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 4M X 16 FLASH 3V PROM, 70 ns, PBGA48
封裝: 6 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-48
文件頁數(shù): 25/90頁
文件大小: 849K
代理商: M29W640GB70ZA6F
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Command Interface
31/90
4.2.8
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command. Read/Reset command does not exit from Unlock Bypass Mode.
4.2.9
Write to Buffer and Program command
The Write to Buffer and Program command makes use of the device’s 32-byte Write Buffer
to speed up programming. 16 words/32 bytes can be loaded into the Write Buffer. Each
Write Buffer has the same A4-A22 addresses.The Write to Buffer and Program command
dramatically reduces system programming time compared to the standard non-buffered
Program command.
When issuing a Write to Buffer and Program command, the VPP/WP pin can be either held
High, VIH or raised to VPPH.
See Table 12 for details on typical Write to Buffer and Program times in both cases.
Five successive steps are required to issue the Write to Buffer and Program command:
1.
The Write to Buffer and Program command starts with two unlock cycles.
2.
The third Bus Write cycle sets up the Write to Buffer and Program command. The setup
code can be addressed to any location within the targeted block.
3.
The fourth Bus Write cycle sets up the number of words to be programmed. Value n is
written to the same block address, where n+1 is the number of words to be
programmed. n+1 must not exceed the size of the Write Buffer or the operation will
abort.
4.
The fifth cycle loads the first address and data to be programmed.
5.
Use n Bus Write cycles to load the address and data for each word into the Write
Buffer. Addresses must lie within the range from the start address+1 to the start
address + n-1. Optimum performance is obtained when the start address corresponds
to a 64 byte boundary. If the start address is not aligned to a 64 byte boundary, the total
programming time is doubled.
All the addresses used in the Write to Buffer and Program operation must lie within the
same page. If an address is written several times during a Write to Buffer and Program
operation, the address/data counter will be decremented at each data load operation and
the data will be programmed to the last word loaded into the Buffer. Invalid address
combinations or failing to follow the correct sequence of Bus Write cycles will abort the Write
to Buffer and Program.
The Status Register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status
during a Write to Buffer and Program operation. It is possible to detect Program operation
fails when changing programmed data from ‘0’ to ‘1’, that is when reprogramming data in a
portion of memory already programmed. The resulting data will be the logical OR between
the previous value and the current value.
To program the content of the Write Buffer, this command must be followed by a Write to
Buffer and Program Confirm command.
A Write to Buffer and Program Abort and Reset command must be issued to abort the Write
to Buffer and Program operation and reset the device in Read mode.
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