參數(shù)資料
型號: M12L128168A_06
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 200萬× 16位× 4個銀行同步DRAM
文件頁數(shù): 41/43頁
文件大小: 804K
代理商: M12L128168A_06
ESMT
Mode Register Set Cycle
M12L128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
2.0
Publication Date
:
Oct. 2006
41/43
Auto Refresh Cycle
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note : 1. CS , RAS , CAS , &
WE
activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQ M
:Don't Car e
HIGH
0 1 2 3 4 5 6
0 1 2 3 4 5 6 7 8 9 10
HIGH
Key
Ra
HI-Z
HI-Z
*Not e 2
* Not e 1
*Not e 3
t
R F C
MR S
New
Command
Auto Refresh
New Command
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