參數(shù)資料
型號(hào): M12L128168A_06
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 200萬(wàn)× 16位× 4個(gè)銀行同步DRAM
文件頁(yè)數(shù): 30/43頁(yè)
文件大小: 804K
代理商: M12L128168A_06
ESMT
M12L128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
2.0
Publication Date
:
Oct. 2006
30/43
Read & Write Cycle at Same Bank @ Burst Length = 4
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (t
SHZ
) after the clock.
3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
t
RCD
t
RC
HIGH
0 1 2 3
4 5 6 7
8
9
10
11
12
13
14
15 16 17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
WE
DQ
DQM
A10/AP
A12
A13
CL=2
CL=3
`
t
RDL
Db0
Db3
Db1
Db2
Ra
Ca
Rb
Cb
Ra
Rb
t
OH
t
OH
t
SAC
t
SAC
t
SHZ
t
SHZ
Write
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
*Note2
*Note3
*Note3
: Don't care
*Note1
Qa0
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qa3
t
RDL
Db0
Db3
Db1
Db2
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