參數(shù)資料
型號(hào)： M12L128168A_06
廠商： Elite Semiconductor Memory Technology Inc.
英文描述： 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述： 200萬(wàn)× 16位× 4個(gè)銀行同步DRAM
文件頁(yè)數(shù)： 23/43頁(yè)
文件大?。?/td> 804K
代理商： M12L128168A_06
ESMT
12. About Burst Type Control
M12L128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
2.0
Publication Date
:
Oct. 2006
23/43
Sequential Counting
Interleave Counting
At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 1, 2, 4, 8 and full page.
Basic
MODE
At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting
Random
MODE
Random Column Access
tCCD = 1 CLK
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
1
At MRS A210 = “000”
At auto precharge . t
RAS
should not be violated.
2
At MRS A210 = “001”
At auto precharge . t
RAS
should not be violated.
4
At MRS A210 = “010”
8
At MRS A210 = “011”
Basic
MODE
Full Page
At MRS A210 = “111”
At the end of the burst length , burst is warp-around.
Special
MODE
BRSW
At MRS A9 = “1”
Read burst = 1,2,4,8, full page write burst =1
At auto precharge of write, t
RAS
should not be violated.
tBDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
Using burst stop command, any burst length control is possible.
Random
MODE
Burst Stop
RAS Interrupt
(Interrupted by
Precharge)
Before the end of burst. Row precharge command of the same bank stops read /write burst
with auto precharge.
t
RDL
= 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Interrupt
MODE
CAS Interrupt
Before the end of burst, new read/write stops read/write burst and starts new read/write
burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
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