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參數(shù)資料
| 型號(hào)： | LXT350PE |
| 英文描述： | PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|LDCC|28PIN|PLASTIC |
| 中文描述： | 的PCM收發(fā)器|單|優(yōu)稅PCM-30/E-1 |的CMOS | LDCC | 28腳|塑料 |
| 文件頁數(shù)： | 15/50頁 |
| 文件大小： | 1197K |
| 代理商： | LXT350PE |
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T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
—
LXT350
Datasheet
15
2.2.2
Transmit Monitoring
The transmitter includes a short circuit limiter that limits the current sourced into a low impedance
load. The limiter automatically resets when the load current drops below the limit. The current is
determined by the interface circuitry (total resistance on transmit side).
In Host mode, the Performance Status Register flags open circuits in bit PSR.DFMO. A transition
on DFMO will provide an interrupt, and its transition sets bit TSR.DFMO = 1. Writing a 1 in bit
ICR.CDFMO clears the interrupt; leaving a 1 in the bit masks that interrupt.
2.2.3
Transmit Drivers
The transceiver transmits data as a 50% line code as shown in
Figure 3
. To reduce power
consumption, the line driver is active only during transmission of marks, and is disabled during
transmission of spaces. Biasing of the transmit DC level is on-chip.
2.2.4
Transmit Idle Mode
Transmit Idle mode allows multiple transceivers to be connected to a single line for redundant
applications. When TCLK is not present, Transmit Idle mode becomes active, and TTIP and
TRING change to the high impedance state. Remote or Dual Loopback, TAOS or any internal
transmit patterns temporarily disable the high impedance state.
2.2.5
Transmit Pulse Shape
As shown in
Table 10 on page 29
, Equalizer Control inputs (EC1 through EC3) determine the
transmitted pulse shape. In Host mode, EC1 through 3 are established by bits 0 through 2 of
Control Register #1 (CR1), respectively. In Hardware mode, pins EC1, EC2 and EC3 specify pulse
shape.
The transceiver produces DSX-1 pulses for short-haul T1 applications (settings from 0 dB to +6.0
dB of cable) or G.703 pulses for E1 applications. Shaped pulses are applied to the AMI line driver
for transmission onto the line at TTIP and TRING. Refer to the Test Specifications section for
pulse mask specifications.
Figure 3. 50% Duty Cycle Coding
1
0
1
Bit Cell
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| LXT350QE | 制造商:LEVEL1 功能描述: |
| LXT351 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation |
| LXT351PE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|LDCC|28PIN|PLASTIC |
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