參數(shù)資料
型號(hào)： LXT350PE
英文描述： PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|LDCC|28PIN|PLASTIC
中文描述： 的PCM收發(fā)器|單|優(yōu)稅PCM-30/E-1 |的CMOS | LDCC | 28腳|塑料
文件頁(yè)數(shù)： 11/50頁(yè)
文件大小： 1197K
代理商： LXT350PE
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
—
LXT350
Datasheet
11
9
7
TRSTE
DI
Tristate
.
HARDWARE MODES:
Connect TRSTE High to force all output pins to the high impedance state.
TRSTE, in conjunction with the MODE pin, selects the operating modes listed
in
Table 5 on page 19
.
HOST MODES:
Connect TRSTE High to force all output pins to the high-impedance state.
Connect this pin Low for normal operation.
11
10
JASEL
DI
HARDWARE MODES:
Jitter Attenuation Select
. Selects jitter attenuation location:
Setting JASEL High activates the jitter attenuator in the receive path.
Setting JASEL Low activates the jitter attenuator in the transmit path.
Setting JASEL to Midrange
2
disables jitter attenuation.
HOST MODES:
Connect Low in Host mode.
12
13
LOS / QPD
DO
Loss of Signal Indicator
. LOS goes High upon receipt of 175 consecutive
spaces and returns Low when the received signal reaches a mark density of
12.5% (determined by receipt of 16 marks within a sliding window of 128 bits
with fewer than 100 consecutive zeros). Note that the transceiver outputs
received marks on RPOS and RNEG even when LOS is High.
QRSS Pattern Detect.
In
QRSS mode
, QPD stays High until the transceiver
detects a QRSS pattern. When a QRSS pattern is detected, the pin goes Low.
Any bit errors cause QPD to go High for half a clock cycle. This output can be
used to trigger an external error counter. Note that a LOS condition will cause
QPD to remain High. See
Figure 11
.
13
16
15
19
TTIP
TRING
AO
Transmit Tip and Ring
. Differential driver output pair designed to drive a 50 -
200
load. The transformer and line matching resistors should be selected to
give the desired pulse height and return loss performance. See
“
Application
Information
”
on page 33
.
14
16
TGND
-
Ground
return for the transmit driver power supply TVCC.
15
18
TVCC
-
+5 VDC Power Supply
for the transmit drivers. TVCC must not vary from VCC
by more than ± 0.3 V.
17
20
GND
-
Tie to Ground.
19
20
24
25
RTIP
RRING
AI
Receive Tip and Ring
. The Alternate Mark Inversion (AMI) signal received
from the line is applied at these pins. A 1:1 transformer is required. Data and
clock recovered from RTIP/RRING are output on the RPOS/RNEG (or RDATA
in
Unipolar mode
), and RCLK pins.
21
27
VCC
-
+5 VDC Power Supply
for all circuits except the transmit drivers. Transmit
drivers are supplied by TVCC.
22
29
GND
-
Ground
return for power supply VCC.
Table 3. LXT350 Signal Descriptions (Continued)
Pin #
Symbol
I/O
1
Description
PLCC
QFP
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
2. Midrange is a voltage level such that 2.3 V
≤
Midrange
≤
2.7 V. Midrange may also be established by letting the pin float.
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參數(shù)描述
LXT350QE 制造商:LEVEL1 功能描述:
LXT351 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
LXT351PE 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|LDCC|28PIN|PLASTIC
LXT351QE 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|QFP|44PIN|PLASTIC
LXT360 制造商:LVL1 制造商全稱(chēng):LVL1 功能描述:Integrated T1/E1 LH/SH Transceivers for DS1/DSX-1/CSU or NTU/ISDN PRI Applications
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