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參數(shù)資料
| 型號(hào)： | LR38666Y |
| 廠商： | Sharp Corporation |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | CMOS digital signal processor |
| 中文描述： | CMOS數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 32/38頁(yè) |
| 文件大?。?/td> | 203K |
| 代理商： | LR38666Y |
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32
LR38666Y
(DV
DD
= 3.3 V, DV
DD2
= 2.5 V, T
A
= 0 to +70C)
PARAMETER
SYMBOL
CONDITIONS
UNIT
NOTE
MIN.
MAX.
Output setup period of CLE, ALE, –WE at reading
(relative to the falling edge of –RE)
Output setup period of CLE, ALE, –RE at writing
(relative to the falling edge of –WE)
Output hold period of CLE, ALE, –WE at reading
(relative to the rising edge of –RE)
Output hold period of CLE, ALE, –RE at writing
(relative to the rising edge of –WE)
"Low" pulse width of –RE
"High" pulse width of –RE
"Low" pulse width of –WE
"High" pulse width of –WE
Input setup period of CFD [7 : 0]
(relative to the rising edge of –RE)
Input hold period of CFD [7 : 0]
(relative to the rising edge of –RE)
Output delay period of CFD [7 : 0]
(relative to the rising edge of CLE, ALE)
T
MASR
2T
MCLK
– 5
ns
1
T
MASW
2T
MCLK
– 5
ns
1
T
MAHR
3T
MCLK
– 5
ns
1
T
MAHW
3T
MCLK
– 5
ns
1
T
SMOEW
T
SOEHH
T
SMWEW
T
SWEHH
4T
MCLK
– 5 4T
MCLK
+ 5
ns
ns
ns
ns
1
1
1
2T
MCLK
– 5 2T
MCLK
+ 5
3T
MCLK
– 5 3T
MCLK
+ 5
2T
MCLK
– 5 2T
MCLK
+ 5
T
MDIS
2T
MCLK
– 5
ns
T
MDIH
0
ns
NOTE :
1. Output load capacity C
L
= 50 pF
1
ns
2T
MCLK
+ 5
2T
MCLK
– 5
T
MDOH
Output hold period of CFD [7 : 0]
(relative to the rising edge of –WE)
1
ns
2T
MCLK
+ 5
2T
MCLK
– 5
T
MDOA
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