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參數(shù)資料
| 型號(hào)： | LR38666Y |
| 廠商： | Sharp Corporation |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | CMOS digital signal processor |
| 中文描述： | CMOS數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 26/38頁(yè) |
| 文件大小： | 203K |
| 代理商： | LR38666Y |
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26
LR38666Y
(DV
DD
= 3.3 V, DV
DD2
= 2.5 V, T
A
= 0 to +70C)
PARAMETER
SYMBOL
CONDITIONS
UNIT
NOTE
MIN.
MAX.
Output setup period of MEMA
(relative to the falling edge of EXCS0Z/1Z)
Output hold period of MEMA
(relative to the rising edge of EXCS0Z/1Z)
Minimum "High" period of EXCS0Z/1Z
Input setup period of MEMD
(relative to the falling edge of EXDACKZ)
Input hold period of MEMD
(relative to the rising edge of EXCS0Z/1Z)
Output delay period of MEMD (relative to MEMA)
Output hold period of MEMD
(relative to the rising edge of EXCS0Z/1Z)
Setup period of EXDACK0Z/1Z
(relative to the falling edge of EXCS0Z/1Z)
Rising period of EXCS0Z/1Z
(relative to the falling edge of EXDACK0Z/1Z)
Hold period of EXDACK0Z/1Z
(relative to the rising edge of EXCS0Z/1Z)
T
MAS
T
CNT20
– 5
ns
2
T
CNT22
– 5
T
MAH
T
CNT21
– 5
ns
2
T
MCC
ns
1
T
MDIS
0
ns
T
MDIH
0
ns
T
MDOA
2T
MCLK
– 5 2T
MCLK
+ 5
ns
2
T
MDOH
T
CNT23
+
2T
MCLK
– 5
T
CNT23
+
2T
MCLK
+ 5
ns
2
T
MCACK
0
ns
T
MACKC
2T
MCLK
– 5 3T
MCLK
+ 5
ns
1
T
MACKH
0
ns
NOTES :
1. Output load capacity C
L
= 15 pF
2. Output load capacity C
L
= 50 pF
T
CNT20
, T
CNT21
, T
CNT22
, T
CNT23
, and each has a
value within the following range depending on the
register setting. T
MAS
corresponds to T
CNT20
in
read cycle and T
CNT22
in write cycle, and T
MAH
corresponds to T
CNT21
in read cycle and T
CNT23
in
write cycle.
T
CNT20
: 1T
MCLK
to 3T
MCLK
, T
CNT21
: 1T
MCLK
to
3T
MCLK
, T
CNT22
: 1T
MCLK
to 3T
MCLK
, T
CNT23
:
1T
MCLK
to 3T
MCLK
: Min. "High" period between read cycles :
3T
MCLK
≤ (T
CNT20
+ T
CNT21
+ 1T
MCLK
) ≤
7T
MCLK
Min. "High" period from read cycle to write cycle
: 3T
MCLK
≤ (T
CNT21
+ T
CNT22
+ 1T
MCLK
) ≤
7T
MCLK
Min. "High" period from write cycle to read cycle
: 3T
MCLK
≤ (T
CNT20
+ T
CNT23
+ 1T
MCLK
) ≤
7T
MCLK
Min. "High" period between write cycles :
3T
MCLK
≤ (T
CNT22
+ T
CNT23
+ 1T
MCLK
) ≤
7T
MCLK
T
CNT23
– 5
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