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參數(shù)資料
| 型號(hào)： | LR38666Y |
| 廠商： | Sharp Corporation |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | CMOS digital signal processor |
| 中文描述： | CMOS數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 12/38頁(yè) |
| 文件大?。?/td> | 203K |
| 代理商： | LR38666Y |
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12
LR38666Y
Clock
The clock supplied to C24MI is doubled in
frequency by an internal PLL and then is used as
the main system clock. This clock is also used by
the NTSC/PAL module in NTSC mode.
The clock supplied to C29MI is doubled in
frequency by an internal PLL and then is used by
the NTSC/PAL module in PAL mode only. The
PAL mode allows clock oscillation. If the PAL
mode is not used, fix the input level to High or Low.
Note that, in NTSC mode, the accuracy of burst
signals (deflection from the specified frequency) for
video output depends on the accuracy of the clock
supplied to C24MI. In PAL mode, the accuracy of
burst signals (deflection from the specified
frequency) for video output depends on the
accuracy of the clock supplied to C29MI.
The clock supplied to COMI is doubled in frequency
by an internal PLL and then is used by the UART,
USART, USB and AUDIOIF modules. Only 24 MHz
frequency can be used.
Note that the accuracy of the clock supplied to
COMI influences the pulse width of the I/O signals.
Supply the clock (synchronized with CCD data) to
TGCLK. Use as low a noise level signal as possible.
Note that accuracy of the clock supplied to TCLK
influences the accuracy of the clock of AUDIOIF.
If TCLK is not used, fix the input level to High or
Low.
Power Supply Pins
Connect low noise power lines to the PLL power
supply pin (PLV
DD
), the PLL ground pin (PLGND),
the DA converter power supply pin (DAV
DD
) and
the DA converter ground pin (DAGND).
Note that PLV
DD
and DAV
DD
are connected to
DV
DD2
, and PLGND and DAGND are connected to
DGND inside the LR38666Y.
Power ON/OFF Sequence
Two power supplies are used with the LR38666Y.
One (DV
DD
) is used for I/O buffer and the other
(DV
DD2
) is used for the core logic circuits.
Power ON : Be sure to turn ON the internal power
supply of DV
DD2
first.
Power OFF : Be sure to turn OFF the I/O buffer of
DV
DD
first.
C
VR
V
REF
R
REF
C
VB
DAV
DD
R
OUT
R
B1
R
B2
DAV
DD
DAV
DD
YCOUT/COUT
Analog Output
DV
REF1/2
DI
REF1/2
VB
1/2
DAGND
Recommended DAC Circuit (Example)
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