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參數(shù)資料
| 型號： | LR38666Y |
| 廠商： | Sharp Corporation |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | CMOS digital signal processor |
| 中文描述： | CMOS數(shù)字信號處理器 |
| 文件頁數(shù)： | 24/38頁 |
| 文件大?。?/td> | 203K |
| 代理商： | LR38666Y |
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24
LR38666Y
(DV
DD
= 3.3 V, DV
DD2
= 2.5 V, T
A
= –10 to +70C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
T
CNT10
– 5
T
CNT14
– 5
T
CNT13
– 5
T
CNT17
– 5
UNIT
NOTE
MAX.
Output setup period of MEMA
(relative to the falling edge of EXCS0Z/1Z)
Output hold period of MEMA
(relative to the rising edge of EXCS0Z/1Z)
Minimum "High" period of EXCS0Z/1Z
"High" hold period of FL_EXOEZ
(relative to the falling edge of EXCS0Z/1Z)
"Low" hold period of EXCS0Z/1Z
(relative to the rising edge of FL_EXOEZ)
"High" hold period of FL_EXWEZ
(relative to the falling edge of EXCS0Z/1Z)
"Low" hold period of EXCS0Z/1Z
(relative to the rising edge of FL_EXWEZ)
Input setup period of MEMD
(relative to the falling edge of EXDACK0Z/1Z)
Input hold period of MEMD
(relative to the rising edge of FL_EXOEZ)
Output delay period of MEMD (relative to MEMA)
Output hold period of MEMD
(relative to the rising edge of EXCS0Z/1Z)
Setup period of EXDACK0Z/1Z
(relative to the falling edge of FL_EXOEZ, FL_EXWEZ)
Rising period of FL_EXOEZ/FL_EXWEZ
(relative to the falling edge of EXDACK0Z/1Z)
Hold period of EXDACK0Z/1Z
(relative to the rising edge of EXCS0Z/1Z)
T
MAS
ns
2
T
MAH
ns
2
T
MCC
ns
1
T
EOEHH
T
CNT11
– 5 T
CNT11
+ 5
ns
2
T
EOCSLH
T
CNT12
– 5 T
CNT12
+ 5
ns
1
T
EWEHH
T
CNT15
– 5 T
CNT15
+ 5
ns
2
T
EWCSLH
T
CNT16
– 5 T
CNT16
+ 5
ns
1
T
MDIS
0
ns
T
MDIH
0
ns
T
MDOA
2T
MCLK
– 5 2T
MCLK
+ 5
T
CNT17
+
2T
MCLK
– 5
ns
2
T
MDOH
T
CNT17
+
2T
MCLK
+ 5
ns
2
T
MCACK
0
ns
NOTES :
1. Output load capacity C
L
= 15 pF
2. Output load capacity C
L
= 50 pF
T
MACKC
2T
MCLK
– 5 3T
MCLK
+ 5
ns
2
T
CNT10
, T
CNT11
, T
CNT12
, T
CNT13
, T
CNT14
, T
CNT15
,
T
CNT16
, T
CNT17
, and each has a value within the
following range depending on the register setting.
T
MAS
corresponds to T
CNT10
in read cycle and
T
CNT14
in write cycle. T
MAH
corresponds to T
CNT13
in read cycle and T
CNT17
in write cycle.
T
CNT10
: 1T
MCLK
to 3T
MCLK
, T
CNT11
: 0T
MCLK
to
3T
MCLK
, T
CNT12
: 0T
MCLK
to 3T
MCLK
, T
CNT13
:
1T
MCLK
to 3T
MCLK
, T
CNT14
: 1T
MCLK
to 3T
MCLK
,
T
CNT15
: 0T
MCLK
to 3T
MCLK
, T
CNT16
: 0T
MCLK
to
3T
MCLK
, T
CNT17
: 1T
MCLK
to 3T
MCLK
: Min. "High" period between read cycles :
3T
MCLK
≤ (T
CNT10
+ T
CNT13
+ 1T
MCLK
) ≤
7T
MCLK
Min. "High" period from read cycle to write cycle
: 3T
MCLK
≤ (T
CNT13
+ T
CNT14
+ 1T
MCLK
) ≤
7T
MCLK
Min. "High" period from write cycle to read cycle
: 3T
MCLK
≤ (T
CNT10
+ T
CNT17
+ 1T
MCLK
) ≤
7T
MCLK
Min. "High" period between write cycles :
3T
MCLK
≤ (T
CNT14
+ T
CNT17
+ 1T
MCLK
) ≤
7T
MCLK
ns
0
T
MACKH
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