參數(shù)資料
型號(hào)： LR38666Y
廠商： Sharp Corporation
元件分類： 數(shù)字信號(hào)處理
英文描述： CMOS digital signal processor
中文描述： CMOS數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 22/38頁(yè)
文件大?。?/td> 203K
代理商： LR38666Y
22
LR38666Y
(DV
DD
= 3.3 V, DV
DD2
= 2.5 V, T
A
= –10 to +70C)
PARAMETER
SYMBOL
CONDITIONS
UNIT
NOTE
MIN.
MAX.
Output setup period of MEMA
(relative to the falling edge of EXCS0Z/1Z)
Output hold period of MEMA
(relative to the rising edge of EXCS0Z/1Z)
Minimum "High" period of EXCS0Z/1Z
"High" hold period of FL_EXOEZ
(relative to the falling edge of EXCS0Z/1Z)
"Low" pulse width of FL_EXOEZ
"Low" hold period of EXCS0Z/1Z
(relative to the rising edge of FL_EXOEZ)
"High" hold period of FL_EXWEZ
(relative to the falling edge of EXCS0Z/1Z)
"Low" pulse width of FL_EXWEZ
"Low" hold period of EXCS0Z/1Z
(relative to the rising edge of FL_EXWEZ)
Input setup period of MEMD
(relative to the rising edge of FL_EXOEZ)
Input hold period of MEMD
(relative to the rising edge of FL_EXOEZ)
Output delay period of MEMD (relative to MEMA)
Output hold period of MEMD
(relative to the rising edge of EXCS0Z/1Z)
T
MAS
T
CNT00
– 5
ns
2
T
CNT05
– 5
T
MAH
T
CNT04
– 5
ns
2
T
MCC
ns
1
T
EOEHH
T
CNT01
– 5 T
CNT01
+ 5
ns
2
T
EXOEW
T
CNT02
– 5 T
CNT02
+ 5
ns
2
T
EWCSLH
T
CNT03
– 5 T
CNT03
+ 5
ns
1
T
EWEHH
T
CNT06
– 5 T
CNT06
+ 5
ns
2
T
EXWEW
T
CNT07
– 5 T
CNT07
+ 5
ns
2
T
EWCSLH
T
CNT08
– 5 T
CNT08
+ 5
ns
1
T
MDIS
2T
MCLK
– 5
ns
T
MDIH
0
ns
T
MDOA
2T
MCLK
– 5 2T
MCLK
+ 5
ns
2
NOTES :
1. Output load capacity C
L
= 15 pF
2. Output load capacity C
L
= 50 pF
T
MDOH
T
CNT09
+
2T
MCLK
– 5
T
CNT09
+
2T
MCLK
+ 5
ns
2
T
CNT00
, T
CNT01
, T
CNT02
, T
CNT03
, T
CNT04
, T
CNT05
,
T
CNT06
, T
CNT07
, T
CNT08
, T
CNT09
and each has a
value within the following range depending on the
register setting.
T
MAS
corresponds to T
CNT00
in read cycle and
T
CNT05
in write cycle, and T
CNT04
in read cycle and
T
CNT09
in write cycle.
T
CNT00
: 1T
MCLK
to 3T
MCLK
, T
CNT01
: 0T
MCLK
to
3T
MCLK
, T
CNT02
: 3T
MCLK
to 15T
MCLK
, T
CNT03
:
0T
MCLK
to 7T
MCLK
, T
CNT04
: 1T
MCLK
to 7T
MCLK
,
T
CNT05
: 1T
MCLK
to 3T
MCLK
, T
CNT06
: 0T
MCLK
to
3T
MCLK
, T
CNT07
: 3T
MCLK
to 15T
MCLK
, T
CNT08
:
0T
MCLK
to 7T
MCLK
, T
CNT09
: 1T
MCLK
to 7T
MCLK
: Min. "High" period between read cycles :
3T
MCLK
≤ (T
CNT00
+ T
CNT04
+ 1T
MCLK
) ≤
11T
MCLK
Min. "High" period from read cycle to write cycle
: 3T
MCLK
≤ (T
CNT04
+ T
CNT05
+ 1T
MCLK
) ≤
11T
MCLK
Min. "High" period from write cycle to read cycle
: 3T
MCLK
≤ (T
CNT00
+ T
CNT09
+ 1T
MCLK
) ≤
11T
MCLK
Min. "High" period between write cycles :
3T
MCLK
≤ (T
CNT05
+ T
CNT09
+ 1T
MCLK
) ≤
11T
MCLK
T
CNT09
– 5
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