參數(shù)資料
型號(hào): LR38666Y
廠商: Sharp Corporation
元件分類: 數(shù)字信號(hào)處理
英文描述: CMOS digital signal processor
中文描述: CMOS數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 19/38頁(yè)
文件大小: 203K
代理商: LR38666Y
LR38666Y
19
NOTES :
1. Output load capacity C
L
= 15 pF
2. Output load capacity C
L
= 50 pF
(DV
DD
= 3.3 V, DV
DD2
= 2.5 V, T
A
= 0 to +70C)
PARAMETER
SYMBOL
CONDITIONS
UNIT
NOTE
MIN.
MAX.
Address output setup time
(relative to the falling edge of FLCE0Z/1Z)
Address output hold time
(relative to the rising edge of FLCE0Z/1Z)
Minimum "High" period of FLCE0Z/1Z
"High" hold time of FL_EXOEZ
(relative to the falling edge of FLCE0Z/1Z)
"Low" pulse width of FL_EXOEZ
T
MAS
T
CNT0
– 5
T
CNT5
– 5
T
CNT4
– 5
T
CNT9
– 5
ns
2
T
MAH
ns
2
T
MCC
ns
1
T
FOEHH
T
CNT1
– 5 T
CNT1
+ 5
ns
2
"Low" hold time of FLCE0Z/1Z
(relative to the rising edge of FL_EXOEZ)
"High" hold time of FL_EXWEZ
(relative to the falling edge of FLCE0Z/1Z)
"Low" pulse width of FL_EXWEZ
"Low" hold time of FLCE0Z/1Z
(relative to the rising edge of FL_EXWEZ)
MEMD input setup time
(relative to the rising edge of FL_EXOEZ)
MEMD input hold time
(relative to the rising edge of FL_EXOEZ)
T
FOCELH
T
CNT3
– 5 T
CNT3
+ 5
ns
1
T
FWEHH
T
CNT6
– 5 T
CNT6
+ 5
ns
2
T
FLWEW
T
CNT7
– 5 T
CNT7
+ 5
ns
2
T
FWCELH
T
CNT8
– 5 T
CNT8
+ 5
ns
1
T
MDIS
2T
MCLK
– 5
ns
MEMD output delay
(relative to the point at which the status of MEMA changes)
MEMD output hold time
(relative to the rising edge of FLCE0Z/1Z)
T
MDOA
2T
MCLK
– 5 2T
MCLK
+ 5
ns
2
T
MDOH
T
CNT9
+
2T
MCLK
– 5
T
CNT9
+
2T
MCLK
+ 5
ns
2
2
ns
T
CNT2
+ 5
T
CNT2
– 5
T
FLOEW
ns
0
T
MDIH
T
CNT0
, T
CNT1
, T
CNT2
, T
CNT3
, T
CNT4
, T
CNT5
, T
CNT6
,
T
CNT7
, T
CNT8
, T
CNT9
and each has a value within
the following range depending on the register
setting. T
MAS
corresponds to T
CNT0
in read cycle
and T
CNT5
in write cycle, T
MAH
corresponds to
T
CNT4
in read cycle and T
CNT9
in write cycle.
T
CNT0
: 1T
MCLK
to 3T
MCLK
, T
CNT1
: 0T
MCLK
to
7T
MCLK
, T
CNT2
: 3T
MCLK
to 15T
MCLK
, T
CNT3
:
0T
MCLK
to 3T
MCLK
, T
CNT4
: 1T
MCLK
to 3T
MCLK
,
T
CNT5
: 1T
MCLK
to 3T
MCLK
, T
CNT6
: 0T
MCLK
to
7T
MCLK
, T
CNT7
: 3T
MCLK
to 15T
MCLK
, T
CNT8
:
0T
MCLK
to 3T
MCLK
, T
CNT9
: 1T
MCLK
to 3T
MCLK
: Min. "High" period between read cycles :
3T
MCLK
≤ (T
CNT0
+ T
CNT4
+ 1T
MCLK
) ≤ 7T
MCLK
Min. "High" period from read cycle to write cycle
: 3T
MCLK
≤ (T
CNT4
+ T
CNT5
+ 1T
MCLK
) ≤
7T
MCLK
Min. "High" period from write cycle to read cycle
: 3T
MCLK
≤ (T
CNT0
+ T
CNT9
+ 1T
MCLK
) ≤
7T
MCLK
Min. "High" period between write cycles :
3T
MCLK
≤ (T
CNT5
+ T
CNT9
+ 1T
MCLK
) ≤ 7T
MCLK
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