參數(shù)資料
型號(hào)： LH28F800SG-L10
廠商： Sharp Corporation
英文描述： 8 M-bit (512 kB x 16) SmartVoltage Flash Memories
中文描述： 8 M位（512 KB的× 16）SmartVoltage閃存
文件頁數(shù)： 30/45頁
文件大小： 328K
代理商： LH28F800SG-L10
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
- 30 -
6.2.3 DC CHARACTERISTICS (contd.)
SYMBOL
PARAMETER
NOTE
V
CC
= 2.7 to 3.6 V
V
CC
= 5.0±0.5 V
MIN.
MAX.
–0.5
0.8
V
CC
+0.5
UNIT
TEST
MIN.
–0.5
MAX.
0.8
V
CC
+0.5
CONDITIONS
V
IL
Input Low Voltage
7
V
V
IH
Input High Voltage
7
2.0
2.0
V
V
CC
= V
CC
Min.
I
OL
= 5.8 mA (V
CC
= 5 V),
I
OL
= 2.0 mA (V
CC
= 3.3 V, 2.7 V)
V
CC
= V
CC
Min.
I
OH
= –2.5 mA (V
CC
= 5 V),
I
OH
= –2.0 mA (V
CC
= 3.3 V, 2.7 V)
V
CC
= V
CC
Min.
I
OH
= –2.5 μA
V
CC
= V
CC
Min.
I
OH
= –100 μA
V
OL
Output Low Voltage
3, 7
0.4
0.45
V
Output High Voltage
(TTL)
V
OH1
3, 7
2.4
2.4
V
0.85
V
CC
V
CC
–0.4
0.85
V
CC
V
CC
–0.4
V
V
OH2
Output High Voltage
(CMOS)
3, 7
V
V
PPLK
V
PP
Lockout Voltage during
Normal Operations
V
PP
Voltage during
V
PPH1
Word Write, Block Erase
or Lock-Bit Operations
V
PP
Voltage during
V
PPH2
Word Write, Block Erase
or Lock-Bit Operations
V
PP
Voltage during
V
PPH3
Word Write, Block Erase
or Lock-Bit Operations
V
LKO
V
CC
Lockout Voltage
4, 7
1.5
1.5
V
2.7
3.6
—
—
V
4.5
5.5
4.5
5.5
V
11.4
12.6
11.4
12.6
V
2.0
2.0
V
V
HH
RP# Unlock Voltage
8
11.4
12.6
11.4
12.6
V
Set permanent lock-bit
Override block lock-bit
NOTES :
1.
All currents are in RMS unless otherwise noted. Typical
values at nominal V
CC
voltage and T
A
= +25°C. These
currents are valid for all product versions (packages and
speeds).
2.
I
CCWS
and I
CCES
are specified with the device de-
selected. If reading or word writing in erase suspend
mode, the device’s current draw is the sum of I
CCWS
or
I
CCES
and I
CCR
or I
CCW
, respectively.
3.
Includes RY/BY#.
4.
Block erases, word writes, and lock-bit configurations are
inhibited when V
PP
≤
V
PPLK
, and not guaranteed in the
range between V
PPLK
(max.) and V
PPH1
(min.), between
V
PPH1
(max.) and V
PPH2
(min.), between V
PPH2
(max.)
and V
PPH3
(min.), and above V
PPH3
(max.).
5.
Automatic Power Saving (APS) reduces typical I
CCR
to
1 mA at 5 V V
CC
and 3 mA at 2.7 to 3.6 V V
CC
in static
operation.
CMOS inputs are either V
CC
±0.2 V or GND±0.2 V. TTL
inputs are either V
IL
or V
IH
.
Sampled, not 100% tested.
Permanent lock-bit set operations are inhibited when
RP# = V
IH
. Block lock-bit configuration operations are
inhibited when the permanent lock-bit is set or RP# =
V
IH
and WP# = V
IL
. Block erases and word writes are
inhibited when the corresponding block lock-bit is set
and RP# = V
IH
and WP# = V
IL
or the permanent lock-bit
is set. Block erase, word write, and lock-bit configuration
operations are not guaranteed with V
IH
< RP# < V
HH
and should not be attempted.
6.
7.
8.
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