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參數(shù)資料
| 型號： | LH28F800SG-L10 |
| 廠商： | Sharp Corporation |
| 英文描述： | 8 M-bit (512 kB x 16) SmartVoltage Flash Memories |
| 中文描述： | 8 M位（512 KB的× 16）SmartVoltage閃存 |
| 文件頁數(shù)： | 12/45頁 |
| 文件大?。?/td> | 328K |
| 代理商： | LH28F800SG-L10 |
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LH28F800SG-L/SGH-L (FOR TSOP, CSP)
4.1
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, word write or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or Word
Write Suspend command. The Read Array
command functions independently of the V
PP
voltage and RP# can be V
IH
or V
HH
.
Read Array Command
4.2
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in
Fig. 2
retrieve the manufacture, device, block
lock configuration and permanent lock configuration
codes (see
Table 4
for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the V
PP
voltage and RP# can be
V
IH
or V
HH
. Following the Read Identifier Codes
command, the following information can be read :
Read Identifier Codes Command
Table 4 Identifier Codes
CODE
Manufacture Code
Device Code
Block Lock Configuration
(NOTE 2)
Unlocked
Locked
Reserved for future enhancement
Permanent Lock Configuration
(NOTE 2)
Unlocked
Locked
Reserved for future enhancement
NOTES :
1.
X selects the specific block lock configuration code to be
read. See
Fig. 2
for the device identifier code memory map.
2.
Block lock status and permanent lock status are output
by DQ
0
. DQ
1
-DQ
15
are reserved for future enhancement.
4.3
The status register may be read to determine when
a block erase, word write, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE#, whichever occurs. OE# or CE# must toggle to
V
IH
before further reads to update the status
register latch. The Read Status Register command
functions independently of the V
PP
voltage. RP#
can be V
IH
or V
HH
.
Read Status Register Command
4.4
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see
Table 6
). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several words in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
Clear Status Register Command
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V
PP
voltage. RP# can
be V
IH
or V
HH
. This command is not functional
during block erase or word write suspend modes.
4.5
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
Block Erase Command
ADDRESS
00000H
00001H
XX002H
(NOTE 1)
DATA
00B0H
0050H
DQ
0
= 0
DQ
0
= 1
DQ
1-15
00003H
DQ
0
= 0
DQ
0
= 1
DQ
1-15
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LH28F800SUT-70 | 8M (512K 】 16, 1M 】 8) Flash Memory |
| LH28F800BGR-BL12 | 8 M-bit (512 kB x 16) SmartVoltage Flash Memories |
| LH28F800BGR-BL85 | 8 M-bit (512 kB x 16) SmartVoltage Flash Memories |
| LH28F800BGR-TL12 | 8 M-bit (512 kB x 16) SmartVoltage Flash Memories |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH28F800SG-L70 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:8 M-bit (512 kB x 16) SmartVoltage Flash Memories |
| LH28F800SGN-L10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Flash EEPROM |
| LH28F800SGN-L100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Flash EEPROM |
| LH28F800SGN-L70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Flash EEPROM |
| LH28F800SGR-L10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Flash EEPROM |
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