參數(shù)資料
型號: LH28F800SG-L10
廠商: Sharp Corporation
英文描述: 8 M-bit (512 kB x 16) SmartVoltage Flash Memories
中文描述: 8 M位(512 KB的× 16)SmartVoltage閃存
文件頁數(shù): 25/45頁
文件大小: 328K
代理商: LH28F800SG-L10
- 25 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
repeated after normal operation is restored. Device
power-off or RP# transitions to V
IL
clear the status
register.
The CUI latches commands issued by system
software and is not altered by V
PP
or CE#
transitions or WSM actions. Its state is read array
mode upon power-up, after exit from deep power-
down or after V
CC
transitions below V
LKO
.
After block erase, word write, or lock-bit
configuration, even after V
PP
transitions down to
V
PPLK
, the CUI must be placed in read array mode
via the Read Array command if subsequent access
to the memory array is desired.
5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure, word writing, or lock-bit
configuration during power transitions. Upon power-
up, the device is indifferent as to which power
supply (V
PP
or V
CC
) powers-up first. Internal
circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious
writes for V
CC
voltages above V
LKO
when V
PP
is
active. Since both WE# and CE# must be low for a
command write, driving either to V
IH
will inhibit
writes. The CUI’s two-step command sequence
architecture provides added level of protection
against data alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP# = V
IL
regardless of its control inputs
state.
5.7 Power Consumption
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.
In addition, deep power-down mode ensures
extremely low power consumption even when
system power is applied. For example, portable
computing products and other power sensitive
applications that use an array of devices for solid-
state storage can consume negligible power by
lowering RP# to V
IL
standby or sleep modes. If
access is again needed, the devices can be read
following the t
PHQV
and t
PHWL
wake-up cycles
required after RP# is first raised to V
IH
. See
Section
6.2.4 through 6.2.6 "AC CHARACTERISTICS -
READ-ONLY and WRITE OPERATIONS"
and
Fig. 13, Fig. 14
and
Fig. 15
for more information.
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