LH28F800SG-L/SGH-L (FOR TSOP, CSP)
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Table 6 Status Register Definition
ECLBS
WWSLBS
5
4
WSMS
7
ESS
6
VPPS
3
WWSS
2
DPS
1
R
0
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 =
ERASE AND CLEAR LOCK-BITS STATUS (ECLBS)
1 = Error in Block Erase or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
SR.4 =
WORD WRITE AND SET LOCK-BIT STATUS (WWSLBS)
1 =
Error in Word Write or Set Permanent/Block Lock-Bit
0 =
Successful Word Write or Set Permanent/Block Lock-Bit
SR.3 = V
PP
STATUS (VPPS)
1 = V
PP
Low Detect, Operation Abort
0 = V
PP
OK
SR.2 = WORD WRITE SUSPEND STATUS (WWSS)
1 = Word Write Suspended
0 = Word Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Permanent Lock-Bit, Block Lock-Bit and/or
WP#/RP# Lock Detected, Operation Abort
0 = Unlock
SR.0 =
RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTES :
Check RY/BY# or SR.7 to determine block erase, word
write, or lock-bit configuration completion.
SR.6-0 are invalid while SR.7 =
"
0
"
.
If both SR.5 and SR.4 are
"
1
"
s after a block erase or lock-bit
configuration attempt, an improper command sequence was
entered.
SR.3 does not provide a continuous indication of V
PP
level.
The WSM interrogates and indicates the V
PP
level only after
Block Erase, Word Write, Set Block/Permanent Lock-Bit, or
Clear Block Lock-Bits command sequences. SR.3 is not
guaranteed to reports accurate feedback only when V
PP
≠
V
PPH1/2/3
.
SR.1 does not provide a continuous indication of Permanent
and block lock-bit values. The WSM interrogates the
Permanent lock-bit, block lock-bit, WP# and RP# only after
Block Erase, Word Write, or Lock-Bit configuration command
sequences. It informs the system, depending on the attempted
operation, if the block lock-bit is set, permanent lock-bit is set,
and/or WP# is not V
IH
, RP# is not V
HH
. Reading the block
lock and permanent lock configuration codes after writing the
Read Identifier Codes command indicates permanent and
block lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.