參數(shù)資料
型號： ISP1761ET,518
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝： 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù)： 90/164頁
文件大?。?/td> 767K
代理商： ISP1761ET,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
30 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
For an overcurrent limit of 500 mA per port, a PMOS transistor with RDSON of
approximately 100 m
is required. If a PMOS transistor with a lower R
DSON is used, the
analog overcurrent detection can be adjusted using a series resistor; see Figure 10.
V
PMOS = VOC(TRIP) = VTRIP(intrinsic) (IOC(nom) × Rtd), where:
V
PMOS = voltage drop on PMOS
IOC(nom) = 1 A
The digital overcurrent scheme requires using an external power switch with integrated
overcurrent detection, such as LM3526, MIC2526 (2 ports) or LM3544 (4 ports). These
devices are controlled by PSWn_N signals corresponding to each port. In the case of
overcurrent occurrence, these devices will assert OCn_N signals. On OCn_N assertion,
the ISP1761 cuts off the port power by de-asserting PSWn_N. The external integrated
power switch will also automatically cut off the port power in the case of an overcurrent
event, by implementing a thermal shutdown. An internal delay lter will prevent false
overcurrent reporting because of in-rush currents when plugging a USB device. Because
of this internal delay, as soon as OCn_N is asserted, PSWn_N will switch off the external
PMOS in less than 15 ms.
Remark: If port 1 is used in OTG mode or as a dual-role device, the analog overcurrent
detection must be used, same on all three ports, because the same bit (bit 15 of the HW
Mode Control register) determines the overcurrent detection type.
7.9 Power-On Reset (POR)
When VCC(I/O) is directly connected to the RESET_N pin, the internal POR pulse width,
tPORP, will typically be 800 ns. The pulse is started when VCC(5V0) rises above VTRIP of
1.2 V.
To give a better view of the functionality, Figure 11 shows a possible curve of VCC(5V0) with
dips at t2 to t3 and t4 to t5. If the dip at t4 to t5 is too short, that is, < 11
s, the internal
POR pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1,
the detector will see the passing of the trip level and a delay element will add another
tPORP before it drops to 0.
(1) Rtd is optional.
Fig 10. Adjusting analog overcurrent detection limit (optional)
004aaa662
REF5V
Rtd(1)
5 V
ISP1761
OCn_N
PSWn_N
IOC
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