參數(shù)資料
型號: ISP1761ET,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 151/164頁
文件大?。?/td> 767K
代理商: ISP1761ET,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
86 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
peripheral, and the A-device assumes the role of a host. The A-device detects that the
B-device can support HNP by getting the OTG descriptor from the B-device. The A-device
will then enable the HNP hand-off by using SetFeature (b_hnp_enable) and then go into
the suspend state. The B-device signals claiming the host role by de-asserting its pull-up
resistor. The A-device acknowledges by going into the peripheral state. The B-device then
assumes the role of a host and communicates with the A-device as long as it wishes.
When the B-device nishes communicating with the A-device, both the devices nally go
into the idle state. See Figure 15 and Figure 16.
9.3 Session Request Protocol (SRP)
As a dual-role device, the ISP1761 can initiate and respond to SRP. The B-device initiates
SRP by data line pulsing, followed by VBUS pulsing. The A-device can detect either data
line pulsing or VBUS pulsing.
9.3.1 B-device initiating SRP
The ISP1761 can initiate SRP by performing the following steps:
1. Detect initial conditions [read B_SESS_END and B_SE0_SRP (bits 7 and 8) of the
OTG Status register].
2. Start data line pulsing [set DP_PULLUP (bit 0) of the OTG Control (set) register to
logic 1].
3. Wait for 5 ms to 10 ms.
4. Stop data line pulsing [set DP_PULLUP (bit 0) of the OTG Control (clear) register to
logic 0].
5. Start VBUS pulsing [set VBUS_CHRG (bit 6) of the OTG Control (set) register to
logic 1].
6. Wait for 10 ms to 20 ms.
7. Stop VBUS pulsing [set VBUS_CHRG (bit 6) of the OTG Control (clear) register to
logic 0].
8. Discharge VBUS for about 30 ms [by using VBUS_DISCHRG (bit 5) of the OTG
Control (set) register], optional.
The B-device must complete both data line pulsing and VBUS pulsing within 100 ms.
9.3.2 A-device responding to SRP
The A-device must be able to respond to one of the two SRP events: data line pulsing or
VBUS pulsing. When data line pulsing is used, the ISP1761 can detect DP pulsing. This
means that the peripheral-only device must initiate data line pulsing through DP. A
dual-role device will always initiate data line pulsing through DP.
To enable the SRP detection through the VBUS pulsing, set A_B_SESS_VLD (bit 1) in the
OTG Interrupt Enable Fall and OTG Interrupt Enable Rise registers.
To enable the SRP detection through the DP pulsing, set DP_SRP (bit 2) in the OTG
Interrupt Enable Rise register.
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