參數(shù)資料
型號: ISP1761ET,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 85/164頁
文件大?。?/td> 767K
代理商: ISP1761ET,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
26 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
count, the ISP1761 will switch back to suspend mode after the specied time. The
maximum delay that can be programmed in the clock-off count eld is approximately
500 ms.
Additionally, the Power Down Control register allows ISP1761 internal blocks to disable for
lower power consumption as dened in Section 8.3.11.
The lowest suspend current, ICC(susp), that can be achieved is approximately 150 A at
ambient temperature of +25
°C. The suspend current will increase with the increase in
temperature, with approximately 300
A at 40 °C and up to a typical 1 mA at 85 °C. The
system is not in suspend mode when its temperature increases above 40
°C. Therefore,
even a 1 mA current consumption by the ISP1761 in suspend mode can be considered
negligible. In normal environmental conditions, when the system is in suspend mode, the
maximum ISP1761 temperature is approximately 40
°C, determined by the ambient
temperature. Therefore, the ISP1761 maximum suspend current will be below 300
A. An
alternative solution to achieve a very low suspend current is to completely switch off the
VCC(5V0) power input by using an external PMOS transistor, controlled by one of the GPIO
pins of the processor. This is possible because the ISP1761 can be used in hybrid mode,
which allows only the VCC(I/O) powered on to avoid loading of the system bus.
When the ISP1761 power is always on, the time from wake-up to suspend will be
approximately 100 ms.
It is necessary to wait for the CLKREADY interrupt assertion before programming the
ISP1761 because internal clocks are stopped during deep sleep suspend and restarted
after the rst wake-up event. The occurrence of the CLKREADY interrupt means that
internal clocks are running and the normal functionality is achieved.
It is estimated that the CLKREADY interrupt will be generated less than 100
s after the
wake-up event, if the power to the ISP1761 was on during suspend.
If the ISP1761 is used in hybrid mode and VCC(5V0) is off during suspend, a 2 ms reset
pulse is required when the power is switched back on, before the resume programming
sequence starts. This will ensure that the internal clocks are running and all logics reach a
stable initial state.
7.7 Power supply
Figure 7 shows the ISP1761 power supply connection.
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